We would like implement a fast adder in xilinx spartan 3 board. I'm looking for a solution to implement high speed adder.
I used to use Spartan 3's a lot. It's now ten years old. There were issues with the internal power distribution in the chip, and it would glitch if too many gates were switching. At 8 bits you should get decent results by just using the + operator in VHDL or Verilog, and then setting a timing requirement on the signal path.
If you build your own full carry lookahead adder, you will still have to set a timing requirement to get the synthesis to optimize it.
The timing requirements are set in the constraints file (ucf). The name of the tool that edits this file depends on the version of the Xilinx tools you are using. If you are using ISE, just double click on the ucf file in the files window.
In Xilinx, whatever the adder topology implemented by you consume more delay than using "+" operator. My choice is using "+" will give better result.
Dear AR Reddy
I hope the attached article link will help you to find the fastest Adder.
ieeexplore.ieee.org/document/8325971/
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