hi all,
i need your help in my research which is based on xilinx system generator by using power minimization techniques in digital and logic circuits , but the problem that i faced is how to implement the techniques such us path balancing , factorization , clock gating , power gating , size gating and Multi-threshold CMOS in xilinx system generator ?
or is there another techniques that can be applicable by using this software (XSG) ?
I think you meant "gate sizing" and not size gating. The answer to your question lies in understanding how to do design using HDL such as Verilog and understanding the relevant options in the synthesis tool.
@c.p. ravikumar , thank you for ur correction and replay
I don't need to design using HDL
I wanna use simulink blocks for xilinix system generator ?
Is there any paper or website that can implement these techniques??
Or how u can help or direct me if it possible ?
@Edward_Md_Fisher
1st thing I want to thank u for ur response
2nd please do u have any projects or thesis belong to ur the explanation, so how I can contact with u directly please I need ur help ????
If you are using Ultrascale + family, you will be able to turn off parts off the chip which you are not using.
There are few methods which can be used for low power designs in FPGAs.
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