How to implement max Log MAP algorithm turbo decoder on FPGA? Simulation is done on MATLAB. What are the next steps to be followed? Do I need to use HDL Coder feature in MATLAB? Is it needed to implement it on Simulink or System Generator first?
Have a look at :: https://au.mathworks.com/matlabcentral/fileexchange/38233-log-map-and-max-log-mapChapter The Modified Max-Log-MAP Turbo Decoding Algorithm by Extrins...
Matlab simulation can help eliminate functional bugs. Now you will have to code the algorithm in a language that RTL compilers can understand, such as Verilog/VHDL.
C.P. Ravikumar Will MATLAB HDL Coder generate the needed VHDL code? Or I have to code Max Log MAP separately in VHDL?
I have not used the Matlab HDL Coder, so I am unable to answer your question. There is no harm in giving it a try. If it can generate VHDL or Verilog, try compiling it into gates.
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