Dear Abdelrahman,

I gave you a previous answer from a direct post to my account, but here I include some details about Ethernet interface. From previous experience working with old Xilinx Virtex5 and Ethernet (10/100/1000 bits/s), here are the ports I needed to connect the FPGA to the Ethernet (extracted from a VHDL code):

Hard_Ethernet_MAC_TemacPhy_RST_n_pin : out std_logic;

Hard_Ethernet_MAC_MII_TX_CLK_0_pin : in std_logic;

Hard_Ethernet_MAC_GMII_TXD_0_pin : out std_logic_vector(7 downto 0);

Hard_Ethernet_MAC_GMII_TX_EN_0_pin : out std_logic;

Hard_Ethernet_MAC_GMII_TX_ER_0_pin : out std_logic;

Hard_Ethernet_MAC_GMII_TX_CLK_0_pin : out std_logic;

Hard_Ethernet_MAC_GMII_RXD_0_pin : in std_logic_vector(7 downto 0);

Hard_Ethernet_MAC_GMII_RX_DV_0_pin : in std_logic;

Hard_Ethernet_MAC_GMII_RX_ER_0_pin : in std_logic;

Hard_Ethernet_MAC_GMII_RX_CLK_0_pin : in std_logic;

Hard_Ethernet_MAC_MDC_0_pin : out std_logic;

Hard_Ethernet_MAC_MDIO_0_pin : inout std_logic;

Hard_Ethernet_MAC_PHY_MII_INT_pin : in std_logic;

So far, for a single Tri-mode Ethernet interface (10/100/1000) you need 27 pins. Not sure if you may share some clock signal between Ethernet interfaces, but I guess you cannot share data. Note that the clock signals are generated by some PLL. If you plan to buy an FPGA board that includes four Ethernet interfaces, such as the one in this link:

https://www.alibaba.com/product-detail/XILINX-Artix-FPGA-Development-Board-A7_1600252132281.html , I assume the manufacturer of this board should provide the user some files, and one of these files is the "constraints file", where there should be a mapping (pin assigments) between FPGA pins and the Ethernet interfaces. Same thing applies to establish the interface between the FPGA and the SFP, but not sure how many pins you need, but I assume there are less pins involved.

According to the DS180 document from Xilinx, the XC7A100T FPGA (from the board with the previous link) includes max 300 I/O pins available, and the "constraint file" from the board manufacturer should list all the pins already used in the FPGA for this specific board.

Regarding the implementation of DNP3 , GOOSE and MODBUS protocols in an FPGA, you may use VHDL or Verilog, but this is very intense task, and you will need complete information on these protocols, regarding the timing, state transition, and structure of each frame.

Regards,

If you are looking for 100Mbit Ethernet you will need an external Phy. There are Phy devices on the market supporting optical interfaces. I'm not aware of a development Board supporting 100Mbit Fiber LC. There was the HyperMax Board available https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/br/ebv-hypermax-brochure.pdf

not sure if this is still available. It contains a Phy with optical support and the respecive fiber interface from Broadcom.

Inside the FPGA you can use the TRI-Ethernet interface:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/exm-net-std-de.html

Dear Abdurrahman Zai̇m ,

The paper in the link contains complete FPGA design and implementation on Xilinx VIRTEX 6 development board:Article FPGA implementation of 1000base-x Ethernet physical layer core

This paper introduces the field programmable gate array FPGA implementation of 1000BASE-X PHY Physical Layer for gigabit Ethernet over fiber optic cable. The implementation is achieved by developing VHDL model for all its building blocks including the physical coding sub layer, PCS, and the physical medium attachment, PMA. The VHDL code is simulated using XILINX ISE14.7 and synthesized on Xilinx Virtex6 FPGA chip. Measured results show that the designed and implemented Ethernet transceiver works successfully at 1.32 Gb/s, 2.5V supply with reduced power consumption.

There is even higher performance chips than Virtex 6 such as Verix 7.

Dear Abdurrahman Zai̇m ,

it would be easier to help you if you provided more specific requirements - how many interfaces you need, whether they need to be 100BASE-T only, or 1000BASE-T(higher latency) also suffice, what exactly you mean by Fiber LC connector, what performance you expect from implementation of mentioned protocols, do you intend to build HW yourself...do you have any specific reason to use FPGA...

In general in order to have RJ45 Ethernet capable port on FPGA, you need (among other things)PHY chip between that RJ45 connector and your FPGA. That will connect to your FPGA via MII(16 wires)/RMII(8 wires)/GMII(25 wires)/RGMII(12 wires) ( + 2wire MDIO) interface depending on PHY type and designer's preference. There are other standards like SGMII and QSGMII with less wires per port, but they usualy connect to transceivers and not GPIO pins.

Fiber optic Ethernet is usually implemented by SFP/SFP+ cage with suitable module inserted. These can be either connected via already mentioned PHY chip(with output interface suitable for optical transceiver) or directly to fpga - usually using transceivers and then consuming one trasceiver per port.

So you can have plenty of interfaces connected to pretty cheap FPGA, but you need to think about it. Not all GPIOs are equal (e.g. you need clock capable pins for certain signals and these are limited resource), some signals need to be grouped in the same bank, you need also enough logic to implement all protocols for all ports.

Then you need set of IP cores for FPGA. At least IP for interface to PHY is necessary. Than you will want MAC probably. Both can be found in many variations on opencores.com for free, or boght from e.g. Xilinx.

Then it depends what other parts of protocol stack you need to have in logic - often UDP, ARP (these are relatively easy to find on opencores and/or implement), TCP(harder to find or implement).

I am not that familiar with protocols you named. But in general, it is much easier to use SW solution than implement it in logic. You can have Microblaze or similar soft-core processor servising all higher level protocols (basically except MAC) using e.g. LWIP stack. You can have several such systems in one FPGA if needed for performance reasons. FPGAs are pretty big and can run MB pretty fast. Impementing all protocols to FPGA logic is possible, but takes time.

There are plenty of dev boards out there, you need to define number and type of interface first and also how much logic and computation power you need.