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Questions related from Bala Murugan s
Dear Professor I am interested to join this project. Kindly consider. https://www.researchgate.net/profile/Bala_Murugan_S2
23 January 2017 2,249 5 View
we have designed a proposed multiplier using Verilog HDL code. Now we want to apply our proposed multiplier for image processing applications. We need procedure or steps or example codes. Can...
21 March 2016 4,296 4 View
Can any one provide me the verilog code to calculate PSNR value for my proposed system. If any one helping the manual (steps) for image processing application, it is highly appreciated
22 December 2015 4,921 2 View
Experiments using IP Core, LCD display, PWM generation, System generator, etc.,
15 October 2015 5,128 4 View
Does Timing Violation in cadence RTL compiler affect the dynamic power report or what is the relation between dynamic power and timing violation?
27 October 2014 5,563 4 View
Can anyone help me to write testbench with varying input probability for unsigned multiplier design, which include .tcf file generation for power calculation
04 August 2014 1,316 3 View
