I designed a 16 bit multiplier using 4-2 compressor and adder. I wrote the verilog test bench code in Xilinx to verify the functionality. My simulation runs quite long time also I am unware of the total simulation time. Can some one suggest me how long it takes for completing the test bench simulation since it takes the combination of 2 power 16. Thanks in advance.
Before starting, I'd like to say that there is nothing as fuzzy and ambigious as 'quite' in engineering. Define quite; hours, days, weeks?
I also see that question as an erroneous one. The run time depends on so many factors other than your RTL, testbench and input vectors. And you want other people to make an estimation for you?
A better approach would be changing your testing style. I think you don't necessarily have to exhaust every single input combination. You can define which input vectors might be more critical and then set your testbench accordingly. The criticality will depend on the type of multiplier you implement.
Lastly, if you want to roughly estimate how long it might take for you to run an exhaustive simulation, you can try running multiple simulations with various number of input vector scenarios. Thereon, you can roughly extrapolate the amount of time needed for your simulation.
Thank you, Mehmet for your reply. Multiplier is an approximate multiplier, so i should compare and calculate the no. error output in approximate multiplier, for that purpose i wish to run all the input combination.
If I understand you, you are using all combinations of a pair of 16-bit numbers in your testbench. That is over 4 billion combinations. It will probably take a long time.
Set up a testbench with 10 combinations and see how long that takes - then multiply it by 400 million.
I suggest you using a parallel array multiplier instead. Very fast and available in many recent FPGAs without the need to use the FPGA logic.
Thank you Mr. Yahyaa. I wish to use newly designed multiplier to compare the performance with current state of art designs. I divided the input combinations into set of intervals and carrying out the simulation but it takes almost 8 hr to complete one set. So, any suggestion to improve the simulation speed it would be grateful to me.
Why is it necessary to simulate verilog? Can't you build a C++ model of the algorithm? You are tying to assess accuracy, not timing - right? This is what everyone in the processor business does to study functionality.
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