I m trying to verify the 64 bit adder (verilog progam) in zynq zedboard 7000. but it has only 8 number of DIP switches and 8 number of LEDs only. How to verify the adder with 64 bits. ie 64 + 64 = 128 bits for input and 65 bits for output. or is there any other method that could be used to verify a 64 bit adder
Aparna Sathya Murthy Thank You madam. I m using vivado 2019. I used testbench to simulate the results. But I m trying to implement it in a hardware kit (ZYNQ Zedboard).
An easy option to do this is to use a virtual input output (VIO) block and an integrated logic analyzer (ILA) block. You can drive inputs to the adder in Zynq using the VIO and monitor the input/output using the ILA.
Check this link
* https://www.youtube.com/watch?v=XsrGc8a3qWI
In the video, the VIO is used to just drive single bits, but you should be able to set up sample depth as 64 bits to drive 64-bit inputs.
(Caution: The video uses a different board, so please be careful to set the pin mapping and voltage level constraints etc. specific to Zedboard.)
Another long route is to make the adder an AXI IP and give data through the Zynq processor. This method is very involved and takes a lot of time to develop the framework and understand it too. The advantage is that this framework can be reused to implement and test more complex designs like image processing etc.
Please check the following links
https://medium.com/@prateek22sri/life-with-an-fpga-3-zynq-ps-pl-axi-basedadder-ece25805e5c6
https://www.youtube.com/watch?v=I0eu_Y3pMmM
https://www.youtube.com/watch?v=Zm3KzhahbUg
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