I created a project in vivado (target language: Verilog, FPGA Device: NEXYS 4 DDR). After successful simulation, synthesis and implementation of all the modules, I am getting Device Utilization Summary as zero(i.e. utilized slices, FFs, LUTs, IOBs, GCLKs = 0).
What can be the possible reason for this?
Xilinx Vivado is not the right tool to get synthesis report. It is a free tool and cannot handle complex circuitry. You can try ISE Web Pack, a complete package for simulation and sysnthesis, which is also free.
Dear fellows, thanks for the answer provided by Edward Fisher . It would be nice to have a snipped section of the code to be more certain about why Saurabh Chaudhury get zero resource utilization. One possible reason is the full usage of variables instead of signals in the code, which affects the synthesis process and next stage, i.e. mapping and then place & route. Regards,
- Badges
- Science topic
- Similar topics
- Mathematics
- Statistics
- Sampling Design
- Sample Size