It probably depends on the quality of your gate oxide, to some extent, but even assuming the highest quality SiO2, I don't think 6 Angstroms is going to give you a very low leakage current. Here is a relevant paper:
http://iopscience.iop.org/0957-4484/21/11/115202
At 1 V bias and 0.65 nm oxide thickness they report leakage currents on the order of 10 A/cm2, which they say is better quality than similar thickness of thermal oxide (they form SiO2 with nitric acid vapor).
Thank you very much John for your answer,
Can Al2O3 (1.5nm) or HfO2 (3.89nm) with the equivalent oxide thickness of 0.6nm be a good alternative option to minimize the gate leakage current ?
Just consider that any leakage current you may face with so thin SiO2 layer is direct tunneling, which can not be eliminated. Even in case of an ideally perfect layer, tunneling would occur.
Increasing thickness, using for example other oxides, may be a route, but you mainly need:
1. the tunneling length be shorter than the physical thickness... possibly much shorter
2. the quality of the layer and of its interface with the semiconductor should be so good to virtually inhibit other conduction mechanisms like Frenkel-Poole etc.
3. the dielectric thickness and its barrier for electrons (or holes) at the interface with the semiconductor must comply with Fowler-Nordheim tunnel conductio, which in the case of SiO2 starts at a transverse field of about 5.5-6.5 MV/cm (for example, even if the direct tunneling is reduced using a thicker silicon oxide film, say 10 nm, the FN onset would occur at about 0.5-0.6 Volt)
Try seeking for a material which is compatible with your processes, have dielectric behaviour equivalent to SiO2 but at larger thicknesses, and have a semiconductor-to-dielectric barrier height (for electrons injection) larger than 3.5 eV.
Thank you very much Giuseppe sir for kind response. It has clarified my doubt.
Leakage current is not only depends upon the oxide(SIO2) thickness,but also depends upon sub-threshold leakage current.
I.e, ILeakage= Isub + I ox,
Where Isubth depends upon Cdep,Vgs as weel as Vth
The thickness of the Silicon Oxide layer required to withstand 20V. safety factor is assumed to be 25%.
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