CMOS circuit design?

20 August 2023 1 9K Report

Design of CMOS circuit to create the signal Vsig. The supply voltage is Vdd and t1 is a delay which is equal to 5ns. The picture is attached.

Nima Shahpari

Hey Meysam Amraee, It seems that you need a monostable circuit. Besides, some kind of charge pump with correct I and C design can give you the timing, then you can easily use an inverter to create a threshold and make the step.

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