Is system operating with low frequency dissipates higher leakage power than system operating with high frequency?
In CMOS/MOS devices, leakage power has no relation with frequency. It is the dynamic power dissipation which is affected by the operating frequency/clock.
Leakage power is mostly due to subthreshold conduction. BTBT and DIBL are quite obvious in deep nanometer devices.
In case of memories, if the hold time is more, more will be the leakage. Of course, there might be some leakage path in the circuit.
dynamic power having relation with frequency of operation. not leakage
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