Can we merge two system generator file using schematic in xilinx ise?

05 May 2015 1 2K Report

I want merge two system generator file in ISE design suite 14.7 so that i can give them separate clock.

You can generate in System Generator two VHDL files for each project then you can insert them in a VHDL or SCH or EDK if you want - I never tried but I am sure it works.

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