I have been doing surface potential modeling for Dual Metal Double Gate FinFET with 20nm channel length. We have designed mathematical model considering effects of source, drain as well as the junction of two metals. But our modeling and simulation result is varying by 0.1V. Also at low gate voltage (0.01V) the step at the junction is not prominent as it should be. So I need to know what kind of SCE are causing these problems and how to rectify them. Kindly find the surface potential graph due to modeling and simulation for different gate voltages.

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