19 Questions 14 Answers 0 Followers
Questions related from Sandeep Kumar
I'm designing a 1T1R memory cell, where the RRAM is modeled using a Verilog-A file. I’ve created a symbol for it and used it in the schematic. The layout of the RRAM is provided by the foundry and...
05 May 2025 5,616 1 View
In synchronous SRAM design, along with SRAM array there is address register and data register. Is these registers are also used for storing the data or they are just for delay?
16 July 2023 2,416 0 View
Why NMOS stacking is more effective in saving leakage power?
05 June 2023 5,580 0 View
Is system operating with low frequency dissipates higher leakage power than system operating with high frequency?
29 May 2023 6,759 3 View
Both SRAM and Flip-flop are volatile memory element. Is there any applications where both are used?
06 May 2023 7,483 1 View
How to calculate the power dissipation for different switching activity in sequential elements?
12 January 2023 9,505 3 View
Like MPFP, important sampling etc.
15 November 2022 668 3 View
I found that, latches can capable to hold the correct data even the data changes slightly before the falling edge of the clock.
13 September 2022 7,545 3 View
At schematic level design i need to add bitline capacitances in HSPICE Simulation. preferred model card is PTM.
21 February 2022 273 3 View
How one can design thin cell layout using cadence virtuoso?
19 January 2022 5,434 2 View
For specific applications different SRAM configuration ( 8T, 9T, 10T, 12T etc.) can be designed. What are the points that one needs to be consider while calculating SNMs?
31 December 2021 7,626 10 View
SRAM, latch and flip-flops are used to store the data. how theses memory elements are differ in terms of their applicability?
11 December 2021 1,674 4 View
How to get butterfly curve for read static noise margins, write static noise margins and hold static noise margin?
09 December 2021 9,443 5 View
In SRAM implementation, while performing read operation we need to precharge the bitline and bitline_bar. Do i need to add explicit bit line capacitance for precharging?
13 November 2021 3,501 6 View
While estimating SET, I need to inject transient fault through double exponential current source as described in literatures. But I can only find exponential current source in SPICE.
03 August 2021 2,645 7 View
I have designed different latch configuration and simulated in SPICE for temperature range -40 to -120 °C . In most of the design, power dissipation increases with temperature but in few it...
29 July 2021 1,720 12 View
For soft-error analysis, due to radiation event at reverse biased PMOS transistor causes 0 to 1 transition while reverse biased NMOS transistor leads to 1 to 0 transition.
27 June 2021 3,447 2 View
Is threshold voltage of transistors decreases with decrease in technology? In 22 nm PTM CMOS model card, i found zero baised threshold voltage is higher compare to 32nm, 45nm......
24 June 2021 6,268 4 View
In my design I require some transistors with high threshold voltage. At schematic level, what changes should I do so that I can get transistors with high threshold voltage.
24 June 2021 8,372 5 View
