I'm designing a 1T1R memory cell, where the RRAM is modeled using a Verilog-A file. I’ve created a symbol for it and used it in the schematic. The layout of the RRAM is provided by the foundry and consists mainly of M1, Via, and M2 layers.

The DRC is clean, but the LVS is failing. Could anyone suggest a way to make LVS pass in this scenario?