At schematic level design i need to add bitline capacitances in HSPICE Simulation. preferred model card is PTM.
The way I'd go about it would be to assess the gate, source and drain capacitances of transistors of the correct size and then count how many of each type are going to be on the bitline of interest. That gives a first, back-of-the envelope calculation.
To actually assess this in simulation and get a much more accurate answer, you might want to set up a simple test bench whereby all the transistor gates are off, you initialise the bitline to 0V and then push current onto it via an ideal current source. By reading the slope of the voltage increase over time you should be able to extract what the simulator thinks the capacitance on that node is going to be.
Of course the real test is when you go for post-layout simulation...
Dear Sandeep Kumar ,
The bit line capacitance can be first estimated by making the lay out of memory cell array. It is determined by how many cells can be connected to this line which conveys the memory cell signal to the sense amplifier. The length of this line must be limited such that its charging must be sufficient to read the logic values of the memory by the sense amplifier without destructing them.
Best wishes
Dear Sandeep Kumar,
After estimating the number of lines and length of the lines connected to the bitline the equivalent capacitance can be estimated based on unit capacitance of each metal.
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