Dear Sandeep Kumar

The SNM is the length of the largest fitted square in the smaller lobe of the butterfly curve (BFC). Since the 6T SRAM is symmetrical, therefore its BFC is also symmetrical. In the case of other cells, (most of which are unsymmetrical), you need to use this definition, and the length of the largest fitted square in the smaller lobe of the BFC will define SNM.

For further read, you may see the following:

1. https://www.researchgate.net/publication/351036478_A_Multi-bit_Error_Upset_Immune_12T_SRAM_Cell_for_5G_Satellite_Communications

2. https://www.researchgate.net/publication/351036478_A_Multi-bit_Error_Upset_Immune_12T_SRAM_Cell_for_5G_Satellite_Communications

Best Wishes,

Ashish!

Dear Sandeep:

You can benefit from this valuable articles about your topic:

"Static Noise Margin Analysis of Various SRAM Topologies"

@https://www.semanticscholar.org/paper/Static-Noise-Margin-Analysis-of-Various-SRAM-Birla-Singh/05beb2421b1f89d0365f2cc497ccc6da0cea764a.

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And this one:

@https://link.springer.com/chapter/10.1007/978-981-10-1023-1_3

I hope it will be helpful..

With my best regards....

Thank You Hassan Nasser and Ashish Sachdeva sir.

Go to "Virtuoso Analog Design Environment" -> Results -> Direct Plot -> Main Form and on the "Plotting Mode" you choose "Append" and plot the value you want.

Hassan Nasser Sir, on what factors does the SNM will depend?

Ashish Sachdeva sir, while calculating noise margin do we need to connect DC source to both the nodes Q and Qb at the same time? for example if RSNM we want to calculate (states are Q=0, and Qb= , WL=Vdd, Bl and Blb are at Vdd), do we require to add postive going noise at Q and negative going noise at Qb at the same time? preferred method is using BFC.

Saurabh Sinha No..!! For BFC, you need to connect the DC source to either of the nodes Q and Qb. then you need to DC simulate and take the output of another node from 0 to x volts.

Best Wishes,

Ashish

Dear @Neti Arora we can say the following

Noise margin is a measure of design margins to ensure circuits functioning properly within specified conditions. Sources of noise include the operation environment, power supply, electric and magnetic fields, and radiation waves. On-chip transistor switching activity can also generate unwanted noise. To ensure that transistors switch properly under specified noisy conditions, circuits must be designed with specified noise margins.

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For more information you can benefit from

This valuable articles:

@https://www.sciencedirect.com/topics/computer-science/noise-margin.

I hope it will be helpful...

Best wishes...

Ashish Sachdeva sir, nowadays SRAM uses multiple input inverters (for different applications) where inputs of inverters are controlled by other nodes (as nodes has also increased). then only adding noise source at Q is enough to plot VTC?

Saurabh Sinha Thank you for asking this question. Hassan Nasser & Ashish Sachdeva sir, how to get VTC at Q by only adding noise at Qb if Q is accepting inputs from other nodes along with Qb?