Hold time is the amount of time that data must be stable after the clock's triggering edge in order for the flop to latch properly. When a flop has a negative hold time, data can change before the clock's triggering edge and be appropriately latched.

Consider the following circuit hold time coming into picture due to the delay involved in the generation of clk' from clk and the time delay transmission gate T_TG takes to turn off. Data should remain stable at the input of T_TG till the time T_TG gets turned off so that it maintains the data the node 1. Now in a case where the T_COMB delay is more than the time it would take for T_TG will turn off (clk' generated from clk), even if data changes at the input T_COMB it will not be propagated to the T_TG input. This scenario gives rise to negative hold time.

So, Negative hold time is not a hard and fast rule. It is determined by the race condition between the data and the clock. If the clock arrives first, the hold time is said to be negative. A positive hold time flip flop can be turned into a negative hold time flip flop by placing a delay in the data stream inside the flip flop.

Hello, colleagues. Please to do not mix negative delay and negative hold(setup) time. Generally negative hold time for latch/flip-flop is post-simulation check of difference between data arrival time & clock arrival time. Sign just means which signal is used as reference vs which signal is faster. Inside latch/flip-flop setup/hold values depend of internal propagation delay of clock & data paths and signal race of saving schematic. Usually negative value come from short data path propagation and buffers chain for clock (t_hold = t_hold_internal + t_delay_clock - t_delay_data).

Denis' answer is correct. Sequential cells can have negative hold properties. This is counterintuitive at first (we tend to think of hold as time after a clock edge, not before an edge), but it is entirely possible and does not cause any problems.

This is not the same as having a negative hold timing during Static Timing Analysis of a full design, which would for sure be a problem.