I am Learning Cadence Virtuoso. But I got stuck after Verifying the Layout Design. Optimization is yet to be done with my layout designs. But I am unable to find desired library for the further processes. Please help me in this regard.
Cadence and Synopsys are the two tools. I prefer cadence because that I what I am used to and they give Universities free licenses. Your question is very vague, what do you mean you are unable to find a library to help with optimization?
Cadence also has a forum where you can post questions about the software and the community is generally very quick to respond.
you must have technology library to proceed further. Normally it is provided by the foundaries like TSMC, UMC etc. Also cadence itself provides gpdk libraries.
I recommend Cadence EDA tool since most of the universities use Cadence.
Thank you Timir and Dr. Sivanantham for your valuable reply.
While registering in Faraday eService for downloading UMC Library, it asks for choosing one of many process libraries like (Low Power RVT/LVT/HVT, Low Leakage RVT/LVT/HVT, Standard Performance Process). Which One I should choose ?
The best EDA Tools for Custom IC Design will be the custom EDA. The most used EDA tools are the simulation tools based on electronics devices or processes models for optimization and design, like Spice and TCAD tools. TCAD tools give the process parameters influence for devices characteristics in order to optimize. The devices characteristics can be used to extract the model parameters to be used in Spice for simulation, optimization and design the custom IC.
I have an EDA tool for automatic cell layout generation from a SPICE transistor netlist description. If you want to give it a try:
https://code.google.com/p/gme-ufrgs/
Apart from Cadence and Synopsys, there is Tanner EDA tool with its L-edit (layout editor). Tanner has been acquired by Mentor Graphics in 2015, so both EDA providers merged their tools. Now you can use L-edit from Tanner and complete the layout verification by Calibre, so both tool worlds are merged and interoperable. Mentor provides also a high-end digital P&R tool called Olympus SoC. Tanner L-edit can be run under Linux and Windows OS, as node-licence or as network-licence.
https://www.mentor.com/products/ic_nanometer_design/place-route/olympus-soc/
There is an affordable EDA tool for layout of VLSI chips (ASICs) as well
as MEMS and can be used for writing also the photo masks. Windows-based.
The tools provider JUSPERTOR is located in south Munich, Germany and attends regularly DAC design automation conference.
https://layouteditor.com/
https://www.juspertor.com/
Other layout tools are: Magic Layout (Linux based):
http://opencircuitdesign.com/magic/
Klayout (Windows and Linux OS based) from Germany
https://www.klayout.de/
openSource (free)
openROAD: digital Place & Route tool design automation conference papers: https://par.nsf.gov/servlets/purl/10171025 https://par.nsf.gov/servlets/purl/10171024 Manual: https://openroad.readthedocs.io/en/latest/index.html Source Code: https://github.com/The-OpenROAD-Project Project Page: https://theopenroadproject.org/
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