Sivanantham S

6 Questions 39 Answers 0 Followers

Questions related from Sivanantham S

What is the advantages of using Synopsys Physical Compiler over Design compiler in Logic Synthesis?

Can any one tell is the Synopsys physical compiler tool is available to the University customers? What are the advantages of using Physical Compiler over Design compiler in logic synthesis phase?

08 January 2016 2,216 2 View

Which tool is best to generate patterns for a LoC delay test?

We have a lot of commercial ATPG tools to generate patterns for specific faults like stuck-at, delay faults. But which tool will provide more reliable patterns which can be used for research purposes?

04 December 2014 7,187 3 View

How much is the cost involved for CHIP fabrication?

We would like to fabricate an IC which includes various students' research works in TSMC90nm Technology. I have two option, 1)MOSIS 2)IMEC, Which choice would be preferred? What will be the...

10 November 2014 1,403 7 View

How can we estimate power (RTL level) in RTL Compiler before performing actual synthesis?

Building RTL Power Models in RTL Compiler

04 September 2014 1,087 6 View

Is Dynamic Timing Analysis mandatory at the Chip Level?

Normally we will perform both STA and DTA at GLN level. However, in general, STA is preferred in the back-end process. Is it necessary to do DTA again after completing the routing process.

24 July 2014 8,289 4 View

How can I invoke ncsim from a RTL compiler prompt?

What is the benefit?

22 July 2014 6,499 2 View