I want to extract the electrical properties of MOSCAP in cadence virtuoso but I don't know the exact method how to measure resistance and capacitance and other properties of MOSCAP
I designed simple LC oscillator using LC components available in pdk, but I am getting DRC and LVS errors with respect to inductor. In schematic the inductor have 3 terminals but in layout it has...
14 February 2024 1,251 2 View
i designed an simple oscillator circuit using MOSCAP but when i tried to do layout i am getting latch up errors , i am also using on chip inductor that is also showing error concerning the metal...
05 February 2024 7,422 0 View
i am using 45nm technology to design LC network, i want to know the characteristics of 3-port inductor available in the 45nm technology such as quality factor, inductance, self resonating...
08 November 2023 7,360 0 View
i am trying to design oscillator using onchip inductor available in 45nm technology in Cadence virtuoso but i am not able to get sustain oscillation due to damping. can anyone tell me how to...
23 July 2023 1,220 1 View
how to design cross coupled oscillator with low power consumption and wit oscillating frequency equal to 100MHz, how to choose RLC values in the tank circuit. is it require to add parallel...
23 July 2023 7,861 0 View
Active inductor are replacement for spiral inductors for their flexibility in terms of tuning inductance , frequency tuning and occupies less area. to design inductor for oscillator what are the...
23 July 2023 6,511 0 View
i am using cadence virtuoso tool 45nm technology for designing LC oscillators with 100MHz oscillating frequency, i wanted to do layout for my design but if I take LC components from analoglib , i...
20 July 2023 1,767 1 View
the main part of LC oscillators is its tank circuit, so i tried to analyze tank circuit seperatly by designing it in cadence virtuoso in 45nm technology. i used onchip LC components (available in...
20 July 2023 4,296 0 View
in adiabatic logic , the circuit is powered by trapezoidal wave but most of the literature mentioned that cross coupled oscillator as Asynchronous power clock generator which is sinusoidal in nature.
20 July 2023 6,243 1 View
i wanted to design ALU using Adiabatic logic , i have resources and when i implemented some basic adiabatic logic like ECRL and PFAL, i observed that , the power consumption depends more on the...
20 July 2023 3,925 0 View
I want to simulate an ISFET Array with a read-out circuit in Cadence Virtuoso which can detect electrolyte from a sample solution.
12 June 2024 6,441 0 View
i make a design topology of mixer For my graduation project working at 28 Ghz on cadence with UMC pdk and get this result S(2,1) 3.5db but when trying to make same topology with another pdk on...
09 June 2024 9,729 3 View
I want to know how to attach the Gate all around FET library can be 3nm to cadence tool. Where we can get the 3nm GAAFET Library.
17 April 2024 2,627 0 View
I have managed to Cadence generic PDK 45nm from the web [1] and found it very good. If somebody could send or link the Generic cadence FinFet PDK "cds_ff_mpt" for studying that'd be great. [1] I...
29 February 2024 5,561 1 View
NW.E.3 : Minimum Nwell enclosure of Stradled NBL>=0.24um
05 November 2023 8,538 0 View
The comparison is made at varying data 8 times, 4 times, 2 times, 1 time and 0 time for 8 active high clock pulses for switching activity factor of 100%, 50%, 25%, 12.5% and 0%.
12 October 2023 4,694 2 View
My Question is when the VG is directly applied to gate of mosfet, in CS amp, though vds> vgs-vth is satisfied, the fet is not in saturation region because vgd> vgs-vth. How to decrease the vgd to...
20 August 2023 3,306 0 View
I want to draw a circuit for a thermistor.
18 August 2023 6,161 0 View
I am troubling to find that in cadence how read current of single bit cell (6T SRAM ) is measured ? i am doing DC simulation for this but how to make Q / Qbr = 0. Does any one help...
31 July 2023 1,641 1 View