Can anyone tell me how to do onchip inductor layout simulation that is available in pdk?

More Shruthi Shivaprakash's questions See All

How to eliminate latch up problem in MOSCAP layout designed in cadence 45nm virtuoso?

i designed an simple oscillator circuit using MOSCAP but when i tried to do layout i am getting latch up errors , i am also using on chip inductor that is also showing error concerning the metal...

05 February 2024 7,422 0 View

How to setup testbench in cadence virtuoso for MOSCAP to measure electrical properties like resistors and capacitance ?

I want to extract the electrical properties of MOSCAP in cadence virtuoso but I don't know the exact method how to measure resistance and capacitance and other properties of MOSCAP

05 December 2023 4,667 0 View

Can you please guide me ,how to simulate or create test bench for 3-port on-chip inductor to get Rs, Cp and Rp values ?

i am using 45nm technology to design LC network, i want to know the characteristics of 3-port inductor available in the 45nm technology such as quality factor, inductance, self resonating...

08 November 2023 7,359 0 View

How to design cross coupled oscillator circuit using onchip inductor and capacitor?

i am trying to design oscillator using onchip inductor available in 45nm technology in Cadence virtuoso but i am not able to get sustain oscillation due to damping. can anyone tell me how to...

23 July 2023 1,219 1 View

How to design cross couples oscillator efficiently ?

how to design cross coupled oscillator with low power consumption and wit oscillating frequency equal to 100MHz, how to choose RLC values in the tank circuit. is it require to add parallel...

23 July 2023 7,860 0 View

Do anyone know about Active Inductor designing and how to analyze the circuit?

Active inductor are replacement for spiral inductors for their flexibility in terms of tuning inductance , frequency tuning and occupies less area. to design inductor for oscillator what are the...

23 July 2023 6,511 0 View

Good afternoon,can anyone give me suggestions regarding LC oscillator design and layout in 45nm technology, in cadence virtuoso tool?

i am using cadence virtuoso tool 45nm technology for designing LC oscillators with 100MHz oscillating frequency, i wanted to do layout for my design but if I take LC components from analoglib , i...

20 July 2023 1,767 1 View

Can anyone please clarify doubt about LC circuit oscillations?

the main part of LC oscillators is its tank circuit, so i tried to analyze tank circuit seperatly by designing it in cadence virtuoso in 45nm technology. i used onchip LC components (available in...

20 July 2023 4,296 0 View

Anyone worked on low power VLSI design using adiabatic logic, i am facing issue in designing power clock generator for adiabatic logic?

in adiabatic logic , the circuit is powered by trapezoidal wave but most of the literature mentioned that cross coupled oscillator as Asynchronous power clock generator which is sinusoidal in nature.

20 July 2023 6,243 1 View

Can anyone working on adiabatic logic circuit design to reduce power consumption in the circuit?

i wanted to design ALU using Adiabatic logic , i have resources and when i implemented some basic adiabatic logic like ECRL and PFAL, i observed that , the power consumption depends more on the...

20 July 2023 3,924 0 View

Thin DNA gel loading sample tips?

I have a 0.25mM thick gel and I am having trouble cleaning out the wells to ensure constant sample application. I usually use a thin syringe to get into the wells and rinse them out with running...

01 July 2024 2,124 2 View

What is the research gap about the title topic?

title topic " Role of Facility Layout in enhancing workplace safety and ergonomics in Batangas State University"

06 May 2024 8,388 1 View

Boost Converter in Continuous Conduction Mode Issues?

Circuit Diagram: https://components101.com/articles/boost-converter-basics-working-design Good day Fellow Electrical/Electronic Engineers I am having a conceptual challenge here when deriving...

06 May 2024 3,289 2 View

How are rms current of diodes calculated in new coupled inductor dc/dc converter?

I want to know how peak and rms current of diodes and capacitors are calculated in terms of output current? if you know good reference with details, please share here or tell me.

04 May 2024 6,277 1 View

Design of compact Battery Charger?

Description : 1. Input rating - Nominal 230V AC. Max 300V AC - Single Phase 2. Output rating - 60V, 15Amp max 3. Efficiency > 90%, 4. Max operating ambient temperature: 50 deg C 5. Volumetric...

02 April 2024 7,338 3 View

How can I export Keepout layer (Board Outline) from CST?

Hi all, I need your help. I want to order my designs as PCB. Most of the PCB manufacturer sites accept for order designs in Gerber format. I converted my designs to Gerber file from CST. But they...

23 March 2024 667 3 View

Why does my raster SVG export have poor quality (blurry)?

Hi all. I'm trying to export some raster data I have created into an .svg file format and the end result turns out blurry for all raster layers. Boundaries for feature layers are crisp. I have...

13 March 2024 2,472 0 View

Via Hole Pad does not show in HFSS 3D Layout?

Hi! Why my HFSS 3D Layout doesn't show the via hole pad even when there is trace connected to it?

05 March 2024 8,295 0 View

High Power Inductor and reactor design?

hi, I need a practical calculation and design for designing passive harmonic filter inductors. and the information about core sizing and considerations for 3-phase system.

09 February 2024 1,913 1 View

How to eliminate latch up problem in MOSCAP layout designed in cadence 45nm virtuoso?

i designed an simple oscillator circuit using MOSCAP but when i tried to do layout i am getting latch up errors , i am also using on chip inductor that is also showing error concerning the metal...

05 February 2024 7,422 0 View

Alan Victor

If you are doing a tapper inductor, Hartley topology, set it up as two inductors which are series. You will need to make the series connections as a pair of via. And place the via connection on another metal layer. The metal and dielectric stack-up needs to be appropriate for you inductor construction.

Whose pdk are you using? Did you check the metal and dielectric stack ups?