Well, it's hard to say. But you have two options, firstly, you have to use the PowerPlay tool from altera to estimate and get the power breakdown in simulation phase. Secondly, you can measure the total current consumed from the main source supply and then multiply that value by the technology voltage of the FPGA chip.

Hello Sumathi,

The leakage current is specified per pin and has typical values of few tens of uA. Your IDE should give you the details in POwer estimation.

However when you talk about PFGA power, it is a bit tricky!

Well a simple calculation as V*I would give you power but what you measure is a current using a multimeter that has certain integration time.

Then kindly note that for PFGA, the core works at different voltage (1-2V) while the I/O block works at much higher voltage range typically 2.7-3.6V. Thus, even if you measure the current, it is a total current of both the core and the I/O block.

Another important point should be noted that the FPGA current is clock dependent.

Datasheets specify current at full speed.Or you should know current per MHz of clock.

The quiescent current and active current is different and you should consider the chip's external loading (due to external circuits).

So, my suggestion is choose your (fixed) clock. Isolate the device from external loads and the measure the device current by powering it at the desired clock. This would give you the total power (core+I/O block).

Hope this helps you!

Some producer of demo boards has embedded 24bit digital current measurement devices, that measure the current drawn for each voltage level of an FPGA. The user can always access the readings. Actually only highly dynamic architectures draw variable currents. Unless, the drawn current remains quite constant for a given architecture.

Mircea,

I agree with you. But I believe, it's the CORE current that will remain constant. On the other hand, have a look at the I/O Block. The currents will be switched dynamically depending upon the rate of I/O activities.

As far as the 24-bit current devices are considered, I am sure, the IEEE1149 Bounday Scan (JTAG) must provide access to these devices or the current data. Normal programming adpaters (the download-cable) might note provide this feature but a LOW-LEVEL access to the JTAG should be able to reveal the current data, in-fact then access to every pin.

Sumathi,

All the switching elements in CMOS FPGA connected to the operating voltage are leaking all the time even those DFFs and LUTs wihich are not configured to operate. So, adding extra configurations to the an FPGA does not affect on the leakage current or passive power consumption of an FPGA. We can say that an FPGA device has a kind of intrinsic static power consumption, witch is allmost same, is it configured or not. Measurement of FPGA's leakage current give you that intrinsic static current. The dynamic power consumption is another story.

Of course, the peripheral loading can lead to relatively variable sourced or sunk currents. But this implies either the variable usage of a lot of pins or relative high- current rated loads on few pins. I never tried this. Anyways, such a study seems quite interesting although it has less to do with finding an unwanted behavior of the core architecture.

You have to measure your total power.

Measure the total current from the main source and then multiply it by the voltage of the FPGA chip.

Do you need to remove the trojan circuit or just to measure its current? I think that measuring the leakage current may help, but is not the best method to detect such trojan curcuits.

Thank you so much to all for your valuable answers..

My next doubt is......Is there any change in leakage power due to trojan circuit insertion, anybody have any experience of it?....Similarly, how to measure dynamic power of FPGA also?

Hello Prasanna sir,

i used Xpower analyzer in xilinx, but i could not see any change in power value, i got 0.060W for all designs.

If you send me a vhdl project and a trojan I will be able to tell!

Sumathi,

Which particular chip or device are you using - Spartan Family? And as I have stated it, have you measured the value on your board or just estimating in your Webpack IDE?

Yes, i selected spartan FPGAs....I used xilinx xpower anayzer (web pack IDE)....

Will the following method useful to you I don"t know. Ground an Input and measure voltage  amplitude at Output (V1). Then include resistor about R=100 MOm between Input and Ground. Measure voltage (V2) at Output. The leakage current will  I(leak)=(V2-V1)/(k*R), where k-amplification/transfer coefficient, R-resistor.