In my view, capacitance and resistance parameter of the net also play major role in digital design. So, you may think about RC value in you design

Hi Sir,

Thank you for your kind reply...

I want to select nets (to insert control block), which controls more no. of outputs.. IN this view, i could not map how RC parameter will help me....Please clarify my doubt... 

Hi Sumathi,

Control elements are not only fan-in and fan-out but also input voltage, operation type and period etc. So, most important thing is what are the objectives we want to achieve. To achieve those objectives what are the things we are doing and most importantly on what environment we are choosing to do those things.

So, please elaborate in which platform you are designing, which type of circuit you are analyzing and finally what you want to obtain from that circuits.

Thanks

For further, need your design objective with type of parameter which is going to analysis.

Slack and critical path also.

Hi Farouq, 

Thanks for your reply.

If possible can you give any related documents....

http://www-inst.eecs.berkeley.edu/~cs150/sp13/agenda/lec/lec17-timing2.pdf

They are important only when the circuit is sequential. 

Thanks Farouq Muhammad for your informative document attachment...

In that document, page no. 10, comparison between virtex 4 and virtex 5 FPGA given for small building blocks.

In that 64-bit adder delay is 2.5ns in virtex 5 FPGA. Can we consider as this 2.5 ns delay is best one at present?

If NO, how can know the best 64-bit adder at present in terms of delay parameter?

Noise margin calculations,  driving current, Power delay product. 

Greetings, 

As far as your question about the best 64-bit adder in terms of delay is concerned: you can create a pipelined 64-bit Adder that can operate faster than 400 MHz (T = 2.5 ns). That is useful only if you need this adder to be accepting continuous bursts of data so that you maximize the adder's throughput (check: "pipelining throughput vs latency").

Pipelining reduces the adder's critical path (the one mentioned above, the one responsible for the 2.5 ns threshold). You should be aware though that 400 MHz is a decent to impressive frequency for an FPGA design, especially if your problem is suitable for data parallelization and/or task parallelization (the FPGA's advantage over CPUs).

If you are an advanced designer you can even better try to design CLB reduction trees to save valuable resources. You can see in the attached paper the use of reduction trees of CLBs instead of a large adders tree. 

Conference Paper A low cost embedded real time 3D stereo matching system for ...