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Questions related from Sumathi Gokulanathan
Hi All, It is well known that Hardware Trojans known so far actually have knowledge of the algorithm and use side channel analysis to leak the keys. To prevent side channel analysis, logic...
21 September 2018 6,463 1 View
Hi all, Does PUF stop side channel attacks?? If so, how does PUF stop side channel analysis based on timing differences or power differences?? Thanks in advance..
21 September 2018 1,256 2 View
Hi all, Is it possible to read-back from an already programmed FPGA? If possible, kindly explain the technique with EDA-CAD tool support for this operation. Thanks in advance.
21 September 2018 5,102 5 View
HI, Good Day to all... In digital design, i want to insert control logic or lock mechanism at internal nets. As far as i know, inserting control logic or lock mechanism at High fan-out nets is the...
28 August 2015 6,907 10 View
Thanks in advance for your replies.
07 January 2015 2,672 7 View
I am using Xilinx ISE 12.2 version. Even after implementation, .ncd file is not available in the project folder. I want to know whether it is because of any setting changes? Do any of you face the...
03 July 2014 9,132 7 View
I want to use synopsys/cadence tools such as synopsys design compiler, synopsys prime time, cadence SoC encounter for place and route and synopsys tetramax ATPG. Are any of the mentioned tools...
29 May 2014 3,358 8 View
I want to measure the frequency of ring oscillator circuit I inserted in my design. I made circuit schematic using xilinx ISE. During behavioral simulation, my circuit is switching its output, but...
15 May 2014 4,725 2 View
I used the xpower analyzer to estimate both dynamic and quiescent power consumption of my design, but when I performed it for different codes, I got the same value for all. I did the .pcf and...
17 March 2014 4,601 13 View
If any excess circuit is been added to my logic as trojan circuit, then it will be visible in any one of the side channel prameters. If it is so, then how to measure leakage current of FPGA to...
20 February 2014 2,492 14 View
In an IC, where no input signals are connected, and no internal clk generator is present, then how to generate a clk inside the IC with the existing circuit to operate a counter?
04 February 2014 8,735 4 View
I know its 16 bit * 16 bit multiplier, but I want to know about its functionality in detail. Any link to know more about ISCAS circuits.
03 February 2014 3,951 2 View
I used x signal as one of the input signal in one verilog module, but during instantiation I used this signal as wire signal. But in top module, x is as wire signal. Can I give x signal as input...
29 January 2014 218 3 View
