Unfortunately, there does not exist a tool that is able to convert a bit file back to vhdl netlist.  The content of a bit file can easily be decoded, it consists of commands for internal configuration port and data frames (this is valid at least for FPGAs from Xilinx), see for example UG470, page 99. It is even possible to determine content of the LUT tables (see ZyEHW), howewer, the majority of data frames remain unknown.

http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf

https://github.com/dobairoland/ZyEHW

.bit file contains binary information and .netlist file contains logic gates and its interconnection. According to me converting .bit file to netlist  file is not at all possible

As far as I remember there is a paper that covers how to obtain the netlist from the bitstream: "From the bitstream to the netlist"  by Jean-Baptiste Note and Éric Rannaud (http://dl.acm.org/citation.cfm?id=1344729) or https://www.researchgate.net/publication/200065272_From_the_bitstream_to_the_netlist

Another paper is "BIL: A tool-chain for bitstream reverse-engineering" by Florian Benz et al. (http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6339165). You can get the open source of the project in the following URL: https://github.com/florianbenz/bil/

Hope this helps

Conference Paper From the bitstream to the netlist

I would like to know why you need to do this? Perhaps knowing the answer will give other, simpler ideas on how to solve your problem.

I want to propose an idea to detect FPGA tampering based Hardware Trojan attacks. Regarding this, i want to convert configuration bitstream data to netlist....

@ to Aurelio Morales Villain eva

Though it's a reply to very old post..

As you suggested, I read about the tool called “debit” tool proposed by Note et al. to generate the netlists from the bitstream. However, it seems that "debit" tool is not very reliable and does not support advanced families of Xilinx FPGAs (e.g. Ultrascale FPGAs). It is also unable to extract encrypted bitstreams, which are more like to be used in mission-critical applications. Kindly suggest the solution in that case.

@ Sumathi Gokulanathan

That's a very old post. Since the paper is from 2008, you cannot expect to support new device families from Xilinx. Not sure if there is a new version of the approach by other researchers. Though, the format in bitstream is very similar in device families specially in high end FPGAs (Virtex). Very difficult to get the netlist if the bitstream is encryted.