The short answer is "Yes.". The long answer depends on the FPGA vendor. For examples, XILINX state on their website that:

"The following Readback properties are available for the Generate Programming File process for FPGA devices. Readback is the process of reading back data from the FPGA device to verify that the design was downloaded properly.

• Security. Specifies the design security by selecting whether or not to allow the readback and reconfiguration of the device. After the FPGA design has been configured, the FPGA configuration data can be read back and compared with the original configuration data. Also, the device can be reconfigured with a different bitstream. For increased design security, select either Disable Readback or Disable Readback and Reconfiguration. Select a Readback option from the drop-down list."

If the code was programmed with readback option, then, yes, you can.

Adding to the colleague above you can look at discussion thread of similar question in the link:https://www.edaboard.com/showthread.php?143407-How-to-readback-from-FPGA

You can ask your question in EDABOARD to get more specific answers.

Best wishes

It is possible, read the configuration file stored in PROM

Just to expand on Svetoslav's answer, it also depends on the model. Almost all FPGAs from 10 years ago had the readback option, now it became a security concern more than ever, and the option has either been removed or disabled by default.

This question also relates to how the bitstream is stored internally to the FPGA. Flash-based devices are non-volatile, and will keep the bitstream on power-off. SRAM-based devices will not, but an auxiliary ROM might be present which holds the bitstream.

@ Sumathi Gokulanathan

Not only you can read what you downloaded in the FPGA, which is known a readback configuration, but you can also readback what actually is running on the FPGA, with readback capture. Both are availabe from Xilinx from many years ago. The first information is actually what comes from what you have in your hard disk (the bitstream), and this information is saved in the "configuration memory" of the FPGA. The second information is read from actually the memory elements in the FPGA (flip-flops, BRAMs and LUTRAMs), you cannot read combinational functions, and this information can be capture on a single rising edge of the clock, and then save that information in a file. You may read as an example the UG191 document (Virtex-5 FPGA Configuration User Guide) from Xilinx for old Virtex5. It is the most complete document about configuration the FPGAs from Xilinx. For newer families, you can find similar documents. Also, you may read my research papers about this topic.