I'd prefer this way :

integer data_file ; // file handler

integer scan_file ; // file handler

logic signed [21:0] captured_data;

`define NULL 0

reg [31:0] test[115200]; //just example

reg [31:0] test_counter;

initial begin

data_file = $fopen("data_file.dat", "r");

if (data_file == `NULL) begin

$display("data_file handle was NULL");

$finish;

end

end

always @(posedge clk) begin

if(reset) begin

test_counter

// Author: Dr. M. C. Hanumantharaju

`define clkperiodby2 10

module image_tb;

//Declarations

reg [0:0] mem [0:8191];

reg [12:0] mem_addr ;

//integer fp1; //File Pointer

// Instantiate top level design

initial

begin

reset_n = 0;

#20 reset_n = 1;

//i = 0 ;

$readmemh("H:/verilog_input.txt",mem1,0,1343); 

$readmemh("H:/in.txt", mem2,0,65535); //Read the image

fp1=$fopen("H:/imnn_res.txt");

clk = 0;

mem_addr1 = 0;

mem_addr2 = 0;

//#1400000

//$stop ;

end

//#10 clk = ~clk

always

#`clkperiodby2 clk