How to implement CNN on FPGA?

More Jyoti Mishra's questions See All

I need JCPDS file of LSFCO nanomaterial. Can anyone provide me?

Require for Rietveld refinement in XRD.

08 August 2024 3,081 2 View

Why does everyone use vs code?

Visual Studio Code (VS Code) has become a popular choice among developers for several reasons: 1. **Free and Open Source**: VS Code is free to use and open source, making it accessible to...

07 August 2024 7,013 4 View

What is the solvent for 8YSZ nano material?

I need to do some experiment with it in liquid form.

07 August 2024 613 3 View

Can usage of AI tools like chat GPT in research work is recommendable ?

AI tools like ChatGPT can enhance research work significantly when used responsibly and in conjunction with thorough human oversight.

05 August 2024 1,842 3 View

What are the limitations and challenges of using machine learning for predicting concrete compressive strength in practical applications?

Machine learning (ML) has shown great potential in predicting the compressive strength of concrete, an important property for structural engineering. However, its practical application comes with...

03 August 2024 2,546 2 View

I'm optimizing a tetra-ARMS PCR protocol with amplicon sizes: 165bp, 123bp and 93bp. Why, in the gel, only 165bp is visible while I'm expecting all 3?

It's an end-point PCR protocol. I'm using 1.5% agarose gel with SyBR Safe dye and TBE as a running buffer, visualization on BioRad XR+ system. I was primarily thinking of primer efficiency,...

01 August 2024 4,673 4 View

I have no added any resarch paper yet but showing three paper? how to delete it?

I have not addede any paper yet but it has selected 3 papers which are not mine in my account. i want to delete that information. please help me

30 July 2024 3,743 0 View

How to know the b axis of a single crystal?

How to apply magnetic field parallel to b axis of any crystal

29 July 2024 4,083 2 View

?como elimino articulos que no son propios?

eliminoar articulos que son de tu autoria

05 July 2024 2,107 1 View

Any professor of Social Entrepreneurship ?

PhD in Social Entrepreneurship and Digital Technologies

04 July 2024 1,675 2 View

In CNTFET model files,which file to include to do the Monte Carlo simulation ?

I used the CNTFET model Verilog A file from Stanford University to design pcntfet and ncntfet

18 March 2024 7,338 0 View

How perform subpixel level measurement of deformation using image processing?

Hi, I am working on subpixel level measurement of deformation using FPGA with the help of image processing technique. Can anybody suggest me the steps to be followed? As per citation pixel level...

14 March 2024 4,078 0 View

Is it possible to develop an ML algorithm for NTC, that works at synchronization of line speed (below 30 ms) using FPGA?

Is it possible to develop an ML algorithm for NTC, that works at the synchronization of line speed (below 30 ms) using an FPGA board? Like a next-generation firewall.

26 February 2024 6,254 0 View

Suggest me any good journal papers for the efficient NTC on real time traffic using FPGA and ML algorithms?

I am looking for a few good journal papers for my next work, which is used for efficient network traffic classification (NTC) using FPGA and ML algorithms for real-time NTC. It is a kind of...

26 February 2024 4,037 2 View

How do we get spice models or circuit equivalents from Verilog-A code??

If we have the Verilog-A code of a device, but we want to work on PSpice software then how will we get the SPICE model or circuit equivalent from the Verilog-A code??

30 January 2024 2,332 0 View

Are there resources for identifying the circuit elements of an FPGA?

I have been trying to find a resource to identify the circuit element structures (from an optical micrograph) of delidded/decapsulated electronic devices, including the imaged Xilinx Arty A7 FPGA....

13 September 2023 2,765 0 View

How to implement and verify 64 bit adder in zynq Zedboard?

I m trying to verify the 64 bit adder (verilog progam) in zynq zedboard 7000. but it has only 8 number of DIP switches and 8 number of LEDs only. How to verify the adder with 64 bits. ie 64 + 64 =...

04 July 2023 3,687 2 View

Overall zero values in Device Utilization Summary of a Verilog Module?

I created a project in vivado (target language: Verilog, FPGA Device: NEXYS 4 DDR). After successful simulation, synthesis and implementation of all the modules, I am getting Device Utilization...

01 June 2023 4,172 2 View

NCVerilog with 45nm Cadence PDK?

I am using ncverilog with 45nm cadence pdk and i am getting the following error:

05 May 2023 9,303 0 View

Anyone who has worked with the FPGA board Artix Ultrascale+ XEM8320?

I need help in monitoring the ADC(Model LTC2268-14) data which is interfaced with Artix Ultrascale+ XEM8320 board.

27 February 2023 9,687 5 View

Manish Verma

Implementation of Convolutional Neural Network with Co-design of High-Level Synthesis and Verilog HDL | IEEE Conference Publication | IEEE Xplore

Abdelhalim abdelnaby Zekry

Dear Jyoti Mishra ,

You can use the tool kit in the link:https://pypi.org/project/pyverilog/ to convert your design from Python to Verilog.

There may be similar tools!

Best wishes

Dennis Gookyi

If you have time and experience in Verilog coding, you can design your own custom RTL codes. This will lead to a more efficient design when dealing with low-cost FPGA boards.