It's very simple to check if your devices are in saturation, either Pmos or Nmos.
If you are in strong inversion you have to verify that: VDS >= VGS-VTH
If you are in subthreshold you have to verify that: VDS>= 4KT, where K is the boltzman constant and T is the reference temperature of operation. KT = 26mV for room Temp.
Now for finding out if you are in saturation through cadence do the following simple steps. Design and size your topology. Then do a DC analysis through "Analog Design Environment". After the simulation is finished, go to Results-->Annotate--> DC Operating Points. When you do that you will see all the operating points of every device of your circuit next to each of them in the schematic view. There you can see directly the actuall VDS of each transistor as well as it's VDSAT (the VDS demanted for being in saturation). If VDS >= VDSSAT then you are in saturation. Often we go a bit further than the actual limit so as to be safe from process variations...
you can see the operating point of a cmos (nmos or pmos) as explained by Mr.Charalambos but Cadence in window of dc operating points (when you click on an especial device) shows you some numbers at the last lines that means respectively:
if u want to display those values near mosfet , run dc analysis and choose edit-component view and then in dc parameter choose the required value for yours.