This is the verilog code of RS latch. The code is working.
module RS_latch_gate(r,s,q,qbar);
input r,s;
output q,qbar;
wire q_i,qbar_i;
nor (q, r, qbar);
nor (qbar, s, q);
assign q_i = q;
assign qbar_i = qbar;
endmodule
But I want to declare initial values in q and qbar which are 1 and 0 respectively. Where and how to write code inside this code to do that ?
You have to use the keyword initial. However, this works only for simulation purposes.
I think you can't! This is a pure combinatorial circuit and therefore special measures have to be taken if you really want.
If you just want to simulate, use the keyword "initial". For synthesis you should use a register variable "reg" but maybe you should switch to a synchronous design - asynchronous designs are not very good to be used with CPLD/FPGA circuits.
If you use Xilinx then XST will automatically initialize variables for you as per the Verilog standard, but ASIC designs don't allow this, it is a feature of FPGAs only.
Initializing the output ports are not popular method, but if you want you can define them as inout type then inside another file you can make an instantiation of it and then probably inside an initial structure assign the values you want to them.
But you can initial the input as R=1 and S=0, this makes the NOR gate with R and Q' input to generate 0 regardless of Q' value then Q is updated and then it makes the Q data value ready.
in simulation since you have no delay you probably cannot recognize the intermediate glitches, but you can add some delay to see the wave forms are not stable at the beginning.
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