Thank you madam for your reply madam, I want to implement it to incorporate in my design..i need to accumulate fifteen 32-bit floating point multiplier output to reduce rounding error...only single time rounding i should do in order to improve accuracy

Dear Laxmisagar Hs ,

You can implement the accumulation process sequentially as the accumulator used in the arithmetic logic unit in the central processing unit.

You can also process them in parallel by using 16 full adders followed by 8 full adders followed 4 , then followed by two then followed by the final accumulator.

Then you will need five stages. So, in this implementation the time will be reduced to five periods instead of 32 periods for the single accumulator.

There may be more higher speed implementation that may cost more hardware but less time!

Best wishes

There are total 30 features in my dataset, so requires fifteen 32-bit floating point multipliers for FPGA implementation. I think if each multiplier output is added with the previous multiplier output and store it in long interval accumulator for further processing in parallel ...whether it reduces time for data training...