I used x signal as one of the input signal in one verilog module, but during instantiation I used this signal as wire signal. But in top module, x is as wire signal. Can I give x signal as input signal and do simulation?
I tried like this, but its showing that x is not i/o port in top module.
I want to give signal to x port and check for some output port which is also wire signal in top module, is it possible in verilog simulation?
This link will be helpful
http://www.asicguru.com/verilog/tutorial/modules/59/
No......... we cannot write testbench for wire signal, only the I/O ports of the top module can only be simulated..........
If you are using Altera, there is a tool named SignalTap - it can be embedded on the same FPGA and can serve you as a logic analyzer that can help you see internal signals that are not I/Os. In Xilinx there is a tool named ChipScope that serves the same purpose. You should check with your product version which tool is suitable for you. Also, if you have a testbench and are using ModelSim, then you can delve in the internal signals no matter that they are not inputs or outputs of the top module. I do not remember quite well, but maybe the same thing is possible with the Xilinx's ISim as well.
Good luck!
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