Hai Sumathi

can you please tell what type of codes you used(is it a simple logic inside the codes?). If the logic functionality is simple for all the codes and the clock frequency is also same then it will result in the same power

Please try with different clock frequencies(higher frequency) then you can feel the difference in power on the same circuits

Please chk this document

http://www.xilinx.com/support/documentation/user_guides/ug440.pdf

The answer said by Aneesh Raveendran is right. In sometimes we can feel the power difference , if we close and open the Xpower tool. I think the data is not getting updated for different designs, it may be the bug in the tool.

Hi Sumathi Gokulanathan,

Let me first tell you the simple procedure of using the Xilinx XPower Analyzer (for understanding) and then some information on that.

Implement the top module using the Xilinx ISE

Open the XPower Analyzer listed in the Place and Route tab of the Design sub window

After the design gets loaded 100%, in the 'Report Navigator' sub window of the XPower Analyzer, click on the 'By Clock Domain' listed in the 'Details' tab.

A list of the clock signals and the clock driven synchronous signals appears in the window pane, by the side if the 'Report Navigator'.

If your design uses clock, change the value of the Frequency of the clock, in the concerned field. (The default value given is 0 MHz)

After changing the clock frequency to the desired value, click on the 'Update Power Analysis' icon in the Toolbar.

After the update gets finished, click on the summary, listed in the 'Report Navigator', to get the updated power values.

NOTE: To measure the power values at different frequencies, restart the XPower Analyzer to get correct values. If you change the frequency many times at a single run, the power values get added up as the algorithm (according to my knowledge) preserves the previous values of power to add them in calculating the power values of next frequency.

All the best,

Regards

NP.

hi Sumathi

To calculate the power must perform the following steps :

1- Add hdl design and TestBench Files

2-DoubleClick on Implementation Design

3- place & route ---> Generate Post-Place & Route Simulation Model

4- Design: simulation----> Route-Place

5- RightClick on  Simulation Post-Route & Place Model --->Process Properties----> Tick on Generate SAIF File…. (Generate Saif File)----->DoubleClick on Simulation Post-Route & Place Model 

after simulation is finished close windows simulation

Note : Type simulation should be Route-Place

6-Tools---->xpower

Hello to you all, 

I'm using ISE 14.7 and it is imposible to get results diferent than ZERO in the Xpower Analizer report. You could check it out in the attached report, I have the followings warnings & errors in the Xpower Analizer:

WARNING:Power:1337 - Clock frequency for clock net "clk_BUFGP" is zero. WARNING:Power:1369 - Clock frequency for one or more clocks was not found through timing constraints (PCF file) or simulation data.

ERROR:Power:1272 - Power_Manager: Invalid XML file. Please choose an XPA generated XML file.

Someone can give me an example of  a valid UCF file?, I read all the post and the manuals, for example the page 77 of this manual: http://www.xilinx.com/itp/xilinx10/books/docs/cgd/cgd.pdf

I tryed with  all these solutions for my UCF file code and nothing, always the clock & others signals are reporting ZERO Watts, some one can provide me a valid design to test the Xpower Analizer?, thanks in advance!

Hello laura

I said steps , do you all steps done  respectively ?

You can generate the .UCF file later steps to do so.

Consider This ,

Your plan may be so small that  micro -watt power consumption , so in this case will show here zero.

In this case copy of your circuit , for example, 10 times ,  the power consumption calculate , later the power divide into 10

Good idea!, really thanks . .

 Hi 

I am using Xilinx 14.1 . But me not able to generate VCD or  SAIF file. kindly suggest

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I don't have an answer to the above question. Thank you for the links.

I would like to ask what is the error (error interval) for the power estimate computed by XPower Analyzer? Did anybody do real measurements to compute the exact power consumption of the FPGA (for any model, including Zynq 7020, for example, which I currently use) for a specific design synthesized? (various research papers like the one describing the Wattch simulator of Brooks, Martonosi state that power consumption estimate of the processor modeled has error rates of 5-10% w.r.t. real measurements with a meter).