9 Questions 18 Answers 0 Followers
Questions related from Anush Bekal
I have a prototype tested results of a 4-bit ADC for which the FFT spectrum is attached. 2.5V p-p input was used with an input frequency of 100 MHz sampled at 800 MS/s 2.5V p-p input was used...
20 January 2017 8,680 8 View
HI I just found an bootstrapped sample/hold circuit from a text book. I have simulated the same. I need to calculate SNR, SNDR and ENOB for the same Input at 5MHz, sampled at 100MHz How can I do...
12 September 2016 9,585 3 View
Hello All I am working on a 4-bit Binary Search ADC. I have a input of 20Mhz sine wave signal which is sampled at 100MHz (5 times). I have obtained the original input signal at the output end by...
24 September 2015 3,388 6 View
I need a valid reference document which describes Tier I and Tier II conferences Thanks in advance Anush
25 August 2015 1,071 6 View
Hello Just for simplicity I want to avoid the sample/hold circuit and get rid of AC signal. I apply a constant voltage of 150mV at the input to my SAR ADC (test purpose only) Is it possible to...
05 May 2015 2,081 4 View
I am working on 8-bit Asynchronous SAR ADC. It uses one comparator which is needed to operate up to 256 levels. Initially the SAR logic is set to the mid value (128 level) = (10000000)2. An...
29 April 2015 7,505 12 View
Does cadence have an inbuilt sample/hold circuits or S/Track options? Or can somebody suggest a circuit for S/H or S/T for medium speed application with less distortion? I am working on 8-bit SAR...
16 March 2015 1,400 7 View
I want to use a CMOS dynamic latch based comparator for my design. It has a Diff amplifier stage and a latch stage. I am finding difficulty to set the 'w' values in the circuit for simulations in...
21 January 2015 4,757 6 View
I have an FFT plot for a 8-bit SAR ADC which is added as an attachment with this post. I need to calculate the above mentioned parameters. My query is how to plug in the required values in the...
16 May 2014 5,574 3 View
