I have seen in many papers they haven't mention any equation. Choose minimum value of W then simulate it again change the value then check the result what changes appear. 

Hi, generally there is always a trade-off between high-speed and low-power, because high-speed operation requires large currents to be drawn. The preamplifier  therefore needs a differential pair with a high gm. Thus, a large W/L is required as well as for the input transistors of the latch. To reduce the offset introduced by device mismatch you can increase the gate area. For a basic understanding of the design process literature like Razavi's "Design of Analog CMOS Integrated Circuits" would be a good starting point.

Hi, changing W values in the circuit is not the difficult one. You can edit the values directly through device properties or even through Spice netlist. But, Just changing W values like trail and error approach is not advisable. The values to be obtained based on your analytical work, also ensure that it will not violate the foundry design rules. 

Thank you all for your replies

My major area of interest is to make my comparator sensitive to small changes in the input terminals. Does increasing the W value of the tail transistors help me ?

I know that sensitivity is directly proportional to offset. How can i model this. what are the other parameters to be considered when dealing with dynamic comparators

Thanks in advance

You would want the latch stage of your comparator to ideally have a large gain so that It can swing rail to rail, so you would want to have a large value of W/L for the input pair. For low offset, you should ensure that the size of the FET is large enough to make sure that the comparator does not yield false trips for a small input difference. Since your comparator is a dynamic latched comparator, the latch stage will draw 0 quiscent current, so all you need to worry about is the power consumed in the preamp stages (if you have any). Now, with respect to delay, the comparator delay is basically a cap charging delay, so for high speed, essentially you would want the comparator delay to be minimum, which means that you would want a low capacitance at the latch output (so size the switching transistors accordingly). and you would want the switching current to be large. However a large switching current entails large kickbacks, which could further lead to false trips. There are many tradeoffs which you should take of in comparator design. 

Hi everyone,

What would be the best and accurate method to get the offset of single and double stage dynamic latch comparator?

I am applying a very slow ramp at one input and other input is fixed to some reference voltage and for some sampling intervals i am tracking both the outputs when they switch. 

I don't feel this method is reliable so if any body know other method please reply.

Regards

Ashish Soni