I'm not sure about your setup - there's a lot that can go wrong. Thus I'll stick to "real world" applications.

1. I'm irritated by the word "asynchronous" as the classical SAR ADC is a synchronous device.

2. The S/H adds one or more cycles to the clock cycles required by the conversion itself - depending on the bandwidth of the circuit. Violating setup time will result in severe errors.

3. It's not clear how you tried to use the spectrum analyzer. Comparing the unsampled input with the 'reconstructed' output (sampled AND delayed with respect to the input) cannot give any useful results.

4. When it comes to real world applications the output impedance of the S/H and the input impedance of the ADC (especially input capacity) adds to the problems. Having a buffer following the S/H output can improve accuracy - at the cost of additional delays.

You may want to search for TI publications - especially articles by Bonnie Baker who has a lot of experience in the field of ADC and DAC theory and performance issues.

Dear Anush,

Adding to Mr.Dreher, the successive approximation register SAR analog to digital converters are sequential circuits and therefore they must be properly timed. That is you have to be sure that the current event must be finished before you start the following one. It is so that you first sample the input analog signal in a time called the aperture time or the acquisition time, then you start the conversion process by initializing the shift register, read its contents, convert it to analog value and compare it with the value of the sample if it is smaller you increment the shift register by writing one to the second most position of the shift register. If it is larger you write zero in the most signification position of the shift register and one in the second most significant position, Then you read the content of the SAR and the process repeats again till you decide for the the least significant bit. It is c;ear now that the successive approximation needs precise control and timing circuit as it is a sequential circuits.

You have to consult the standard references in the A/D converter literature.

wish you success.

For debugging I would suggest to run the clock of the ADC much slower and check that the SAR conversion finishes in time.

In addition, you can check S(N)(D)R also directly after you sample to see how much distortion you get from the sampling switch.

Both approaches help you analyzing where the problem comes from.

From experience, negative ENOB/SNDR often results when your time window where you take the SNDR by the spectrum(Meas) function is wrong or you sample the value at the wrong place. E.g. when the end time of spectrum(Meas) is after your simulation end time.

Thank you all for ur reply

Just for simplicity I want to avoid the sample/hold circuit and get rid of AC signal. I apply a constant voltage of 150mV at the input to my SAR ADC (test purpose only)

Is it possible to calculate the dynamic parameters (ENOB, SNR etc...) of an ADC using a constant DC signal at the input to the ADC? Is this a right approach ?

Thanks in advance

Dear Anush,

At first i would like to remember a concept for the measurement. It is so that you measure the quantity as you define if . So , when you measure the static parameters of he ADC you have to sick their definition and conditions of measurement.

So, to measure the static parameters of the ADC which are related to its transfer curve you need to connect an ideal DTA converter in its output, inputting a known slow ramp voltage a its input and displaying the the output of the DAC versus the input of  THE ADC. 

Concerning the sampling rate , i must be sufficient to cover at least the number of levels in the ADC. from the he zero voltage to the VFS voltage.

To measure the dynamic performance parameters, it is best measured using a sinusoidal wave input with the intended frequency and oversample it o resolve the noise and distortion. That is fs must be much greater than the input signal frequency.

You must consider that the ADC has highest conversion speed and the the sampling rate must be smaller equal the conversion speed.

Before making any spectrum analysis on the outputs signal of the ideal DAC at the output of the ADC you have to display the signal in time domain. If the signal resembles the input then you adjusted properly your ADC and your test signal.

I examined your attached waveform and i see that it is okay but you displayed only the waveforms for one sample only. 

Before you analyse your signal using spectrum analyzer you must be sure that the ADC outputs the correct waveform.

For more and useful information please go to the link:http://www.mit.edu/~klund/A2Dtesting.pdf

wish you success

@shoiab thnq for ur reply:

I am using a internally generated clock from my comparator which will be used by the SAR logic (avoided external clock).

I am using an 8-bit Binary weighted Capacitive-DAC (non-ideal)

@Abdelhalim Zekry Sir

I am sampling a signal (fs) for a input signal of frequency 500Khz. Now I need 8 clock cycles to completely settle my SAR logic (digital) and attain the correct value of the input signal. This will parallel be transferred to the C-DAC to reconstruct the original sine-wave. But I can see my DAC output clamping to a certain output value and it follows continuously. The waveform is not smooth. Is this the problem occurring for the waveforms for one sample only. 

 Dear Anush,

As i understood from your reply on my comment that the output of the DAC will be clamped to. after one sample. which means that your conversion process is not repeated. This exactly which i observed in your waveforms. You have to resolve this issue such that you observe at the output at least 10 cycles. You expect if your ADC work properly that the output waveform more or less a sinusoidal wave resembling to the great extent the input wave.  If your signal is frequency is 500 kHz. sample it at 10Mhz with sampling time to 100 ns, which is equal to your aperture and conversion time. From the graph your ADC can work at this speed.

If you want to display 10 cycles then you have to take 20 samples per cycles  x 10 cycles = 200 samples.This is an example but it may be better to display more cycles.

please return to me.

Wish you success.

I am working on this now

Abdelhalim Zekry Sir and Sohaib Saadat Afridi Sir . I ll get back after trying your feedbacks

@Sohaib Saadat Afridi Sir

I apply a DC of 500mV and the DAC settles around the same range 152mV.please see my attached file

I just saw this video tutorial on estimating the ENOB

https://www.youtube.com/watch?v=g1MjXj3PQnM

I apply a constant DC voltage of 500mV to my input and plot the histogram at the output of the DAC.. I want to know whether my obtained plot is within the game or is it distorted?

how can i calculate the ENOB using the std.deviation data for the obtained plot ?

@Sohaib Sir

If u see my waveform file that's attached, first waveform is the DAC out put. I mean reconstructed analog output waveform(dac_out)