Does cadence have an inbuilt sample/hold circuits or S/Track options?
Or
can somebody suggest a circuit for S/H or S/T for medium speed application with less distortion?
I am working on 8-bit SAR ADC's
Thanks in advance
Anush
in Cadence there is no sample and hold circuit, but instead you can do it from circuit element
its just a switch (transistor) followed by a buffer :)
regards
@samer : I have some issues with that . I get a lot of spikes on my output FFT spectrum. not able to recognize what exactly is the problem
@diomadson
Sir, macromodel is prefered. I need to do the simulation as of now
In the Cadence AMS Environment User Guide page 157 you do have a example of a complete S/H in veriloga.
It can be useful.
ftp://ftp.sitsemi.ru/pub/Cadence/amsenvug.pdf
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