To calculate sample/hold circuit You need to know it's input resistance and hold capasitor capasity (tRC=R*C). The sampling period T must be more greater relative to tRC.

For example: 10 bit ADC error A/dA=210=1024 leeds to T~tRC*1024. This is the main problem of HighSpeed ADC.

Dear Anush,

I would like to add to  the Vladimir answer, that the error due to sampling is considered as a noise and distortion. To be more clear the sample and hold circuit outputs at a sampling time instant  nTs a value y(nTs) while the inpu is x(nTs) . As clear from you waveform the two values are different. They are only approximately equal.

So, the noise and distortion is the difference y(nTs) )=y(nTs) - x(nTs) ,

So building a difference time sequence extending a number of complete cycles of the input wave form can be used to evaluate the noise and distortion simply by by squaring and averaging the difference function along the observation time T=MTs.

That is N+D= sum y(nTs) ^2 over all Msamples /M,

The signal to noise and distortion can be determined by dividing the signal power to the noise and distortion power as defined by the above equation. That is,

SNAD RATIO=  sum x(nTs) ^2 over Msamples/M / N+D,

In order to separate the noise from distortion you need only to transform the output sampled sequence to frequency domain using the discrete fourier transform or the fast Fourier transform. The input tone and its harmonics will be apparent in this domain in addition to the noise floor. One can then determine the mean square value of the fundamental and the mean square value of the harmonies and the  mean square value of the noise floor. One can get also the spurious free difference

which represents the ENOB. However, the effective number of bits has only meaning for a complete A/D converter.

Wish you success

Dear Zekry sir and Kubov sir, thank you so much for your valuable inputs