In our current design of linear binary current steering low-noise CMOS slowDAC, we converged in the use of long channel NMOS transistors. Indeed, a low noise, lower than 10pA/√Hz at 100µA, and good matching of the weights of the binary DAC leads to the use of long channel NMOS transistor in the design of binary coded current mirrors.
It seems better to increase L than W to improve the current mirror matching looking at Monte Carlo Simulations.
NMOS sized with L as long as 20 µm for a W of 8 µm is considered. Assuming that such long channel NMOS transistors are unusual (?) in VLSI design ... have you experienced the use of long-channel transistors in VLSI DAC design? Any papers, or review about the use, and justifications, of long channel MOS transistors for ASIC design?
There is no unusual dimension in analog design. The question is what is constrained by technology.
In classic CMOS (would say process older than 130nm) channel can be any long. Lower nodes (but not modern ones) like 28-130nm might has limit for channel length and also pocket/halo doping. In such case matching is length dependent and the best approach is to use stack of large number minimum length MOSFETs. Modern technologies (FinFET and FDSOI) has more constraints.
Nevertheless, DAC resolution is determined by matching and for given current designer has to maximize inversion region of current source and the only way to achieve it is by decrease W/L ratio and increase area.
So, back to your consideration 8um/20um dimensions are common rather than unusual.
Similar and even much longer and narrower transistors are used for current compensation / charge resetting in low noise charge sensitive amplifiers implemented as CMOS ASICS for readout of nuclear detectors.
Perhaps you should look at
" The active resistive feedback network uses an on chip nanoampere current source for biasing and a 4-bit D/A converter for user selectable feedback resistance and detector leakage current compensation up to 15 nA "
in
A Low Noise CMOS Charge-Sensitive Preamplifier with Pole/Zero Compensation for a Neutron Detection System.
Steven Curtis Bunch, University of Tennessee - Knoxville
https://trace.tennessee.edu/utk_gradthes/1514/
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