Application-specific integrated circuit (ASIC) designs for space applications must address radiation environments that can changes stored values in registers. Indeed, high-energy particles can set up a sensitive memorie node : we speek about SEU - single event upsets. RHBD - Radiation Hardened by Design - methods usually uses TMR - Triple Modular Redundancy - to suffer from no error one SEU. More than one SEU requires an intermediate correction which are sometimes addressed by a complementary SRL - Self Restoring Logic - methods. However, this last self-correction method requires a clock (and even 3, some times) to initiate the correction.

Looking for a similar correction in a quiet mode (without clock), we are interested to any circuit diagram showing a kind of "asynchronous SRL method" with no clock used to correct a TMR static register (used as a memorie).