Hello,
I have very high gate leakage currents in graphene field effect transistors. Graphene transistors are covered by Al2O3 (80nm). Graphene is on top of SiO2(285 nm)/p-Si. Al2O3 and SiO2 was etched by plasma etching.
I think that it might happen due to plasma assisted oxide damage. However, in the literature, this problems generally appear in thin oxide layers (
Why was the bottom SiO2 etched? Is the leakage present in both top and bottom gates? How did you deposit the alumina?
Dear Tanuj,
I etch trough Al2O3 and SiO2 to make bottom gated graphene transistors. I don't have top gate, but leakage present in bottom gate (where oxide layer is SiO2). I deposit Al2O3 by ALD, having seed Al(2nm) seed layer.
I check DC bias during etching it was 390 V and 250 V for Al2O3 and SiO2 etching. I think high bias during AL2O3 etching cause oxide damage.
Sincerely,
Salamat
I'm unable to understand your device structure. Do you have a photograph or a schematic?
I have a few questions:
If you have graphene on SiO2 substrate, and you cover it with alumina, why do you need to etch either of the oxides to make the device? Unless you're trying to make side/edge contacts to graphene, in which case you should only need to etch the top oxide.
If you're not trying to make top gated devices or edge contacts, why deposit the alumina in the first place?
Are you etching the entire thickness of the SiO2 near the device area? If so, is there SiO2 left between your contact electrodes and the underlying Si substrate?
My optical microscope image is attached. I am fabricating bottom gated graphene transistor. I use Al2O3 layer to passivate the surface, because H2O/O2 from the ambient p-dopes graphene channel. I am etching Al2O3 and SiO2 away from my structures and channel (and all structures where masked by thick resist while etching ) to use p-Si ( which is substrate material) as bottom gate.
So you deposit the contact metal first, then passivate with alumina? Because if you do it in the opposite order, and deposit the contact metal after etching the SiO2, you are shorting to the Si substrate.
What is the leakage current?
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