Hello,
I have a problem. My graphene( on top og SiO2 (285nm)/p-Si) FETs are covered by Al2O3 to passivate them from ambient. Than, I use plasma etching for opening back gate where Al203 (Cl2, BCl3) and SiO2 (O2, C4F8) ere etched. After I observe large gate leakage. I suspect this was due plasma etching because I measure the samples which was not plasma etched gate leakage is extremely low. Total dielectric thickness is 285nm (SiO2) and 80nm of Al2O3.
Please, suggest any solution to this issue. Have anyone faced with this problem before?
Thank you!
Hi Salamat,
What kind of etch system are you using? Is it RIE or ICP? In general high bias etching (ion energy) will create etching damage which results in gate leakage. RIE etchers are capacitive RF systems and there is no decoupling between ion density and kinetic energy of the etching species. With ICP you have more freedom and there is decoupling of ion density and ion energy and it is possible to etch with low ion energy but keep a high etch rate (ion density). Lowering the bias in both systems can be achieved by ethcing at lower power levels or higher pressures. The disadvantage is you will get less directional etching and etch profiles might change from vertical to reentrant (depending on what chemistry you are using). Hope this advise will help.
Peter
Hi Peter,
I am using ICP RIE. As far as I understand plasma induced oxide damage is observed in thin oxide layer. in my case layer are relatively thick 80nm Al2O3, and 285 nm SiO2. Is it still possible to observe this effect?
Thank you,
Salamat
Hi Slalmat,
I understand your graphene is on top of the SiO2 and you protect it with Al2O3 where you need to etch through. I also assume wehn you etch through the Al2O3 you will etch into the SiO2. So you might have etch damage both in the Al2O3 and SiO2. As you mentioned usually the damage is restricted to a thin layer. Is there a possibility you can do a wet etch of some of the SiO2 after wards. Usually this removes the damaged layer.
In the past I etched InP mesa's with a SiO2 mask on top and we also saw etch damage on the sidewalls of the InP. This damage was ca 50-80 nm into the InP (from the side of the InP) and could be seen by SEM. Your Al2O3 is 80 nm thick and might be too thin to protect the graphene. Is there any of the graphene not protected by Al2O3?
Hi Peter,
Yes, my graphene is on top of SiO2 and covered by Al2O3. Contact pads are not covered by Al2O3 but on top of SiO2. And there is a gate which is hole though Al2O3 and SiO2. All other area is covered. I can't etch SiO2 because it is between graphene and p-Si.
Sincerely,
Salamat
Hi Salamat,
Is there a possibility you drop the bias voltage during etching and increase the ion density with the ICP coil power so you can maintain a good etching rate. The damage is usually induced by high energy ions, not by the number of them reaching the surface. Usually as you dropping the ion energy this will lead to less directional etching. But I don't know if the sidewall profile of the etch is that important for your purpose? At least you can check whether this helps for the gate leakage. Alternatively, you could etch the last part of your etch with lower bias voltage so that the leakge gets less.
regards,
Peter
Thank you for advice, Peter. I was doing Al2O3 etch at RF power 150W and ICP 800W, and SiO2 etching RF Power 200W, and ICP 2500W. Today, I checked the bias during deposition and it shows 390V for Al2O3 etching and 250V for SiO2 etching. It seems that high bias during Al2O3 etching cause damage to oxide. So, as you mentioned I will reduce power. Sidewalls are not important for me, so I can optimize my process accordingly.
Regards,
Salamat
Hi Salamat,
These DC-bias voltages are very high for these etching purposes. Try to get them down to more typical values of 25-50 V range and see if it affects the leakage currents. You will see a drop in etch rate though. You might even need to adjust the coil powers but try to keep them unchanged if possible.
regards,
Peter
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