In Verilog, the code can come out of the loop using Break and Disable keywords, but these two keywords are not synthesisable. You can overcome this challenge by effectively using State Machines. 

For example:

----------------------------------------------------

always@*

case(current_state)

Ready: // Do stuff next_state=State0;

State0: begin  (Do stuff) if(condition) next_state=Final_state; else next_state=State1; end

State1: //Do stuff next_state=Final_state;

Final_state: Done=1'b1;

default:next_state=Ready;

endcase

-------------------------------------------------

Hope this helps!

Hi 

You can used a conditionoutside the loop  to activate it, and than change this condition inside loop

You probably didn't need the loop to begin with. As poster above mentioned, an FSM can handle what you are trying to achieve.

Thank U all...but can we not do it without state machine.?

You can do it with code that doesn't look like a state machine... but has the same ability to express logic as one FSM. No difference at all. In fact, it is probably best to adhere to FSM coding standards as it will make it easier for the synthesis tools to recognize what you are coding and optimize it properly.

Thank you all for nice answers but my problem statement is little bit different which is given below-

I need to read one memory location which has 10 locations in that if corresponding condition is satisfied than I need to some process and come out from for loop.For example If i=2 my if condition is satisfied no need to process for loop.

For(i=0;i

You should be using an FSM for that. That simple.

You can put one more condition let say j=1 outside for loop to run for loop and change the value of j inside for loop when you dont want to come out of for loop. FSM is the best approach to solve these cases.