NO. If you can really see it, it's mechanical fragmentation. The defects mentioned in the paper are atomic defects (Si dangling bond).

I know that the defect density influences the carrier transport and is therefore crucial for photovoltaic devices.

Dr A.Ouerdane

Thank you Martin for the comment, I totally agree

We describe microscopic defects relevant for electronical quality (not mechanical properties) of a very particular type of material - thin film hydrogenated silicon. To solve the problem with your films one should try to examine the mechanical properties of these films and adhesion to the substrate.

There are so-called principle of epitaxy: if the lattice constants of the substrate and film are more than 10%, in this case the interface will be of poor quality and have reduced adhesion, which leads to problems after annealing. Thus it is possible to preliminarily evaluate the difference in the lattice constants of the substrate and the metal film. If the difference is less than 5%, it is likely and perhaps  adhesion will be normal and the film will not crack and peel off. Also, the thickness of the film greatly influences on the film quality and adhesion. I think that so to avoid cracking of the film after heat treatment could have been introduce an intermediate layer which reduces the difference in lattice constants either during film deposition to make the intermediate annealing.

No. defect density has nothing to do with this. Just too different thermal prperties of the substrate and the film you want to deposit. You might be able to aleviate the problem by using on or more intermediate layers that will offer gradual transition.

For a layer used to elaborate transistors I confirm that several reasons why reducing the interface defect density is important:

•Traps can terminate electric field lines from the gate or contribute to them so the result is an altered threshold voltage.

•The trapped electrons and holes in these states can act like charged scattering centers for the mobile carriers in the surface channel and thus lower their mobility.

•The interface states can serve as generation-recombination centers, therefore adding a surface leakage current to the device.

In order for a transistor to have reproducible and predictable characteristics, it is important to have fabrication processes that minimize interface defect density. To reduce interface defect density, devices were oriented on planes rather than or

Read more on this site:

The design and development of nanocrystalline silicon thin film ...

archives.ece.iastate.edu/archive/.../01/Binder1.pdf‎

Dr A.Ouerdane

SOG crack is a general issue after curring, you need to notice the curing steps and temperature setting. Ususally, it will happen at the corner of big pattern due the stress concentration. Therefore, the curing process is very important. It can not use in semiconductor product if there has crack inside. So, we shall not regard these crack as "defect" or "defect density". The real defects happen in SOG is the bubble inside, sometime, it is non-killing defect, however, if the bubble is too large or can't disappear after curing, it may lead to another disaster. If we can not debug the big bubble issue, it is suggested to change SOG material. If you use SOG in the IMD process, please refer my paper, degas process is very important (like the curing process in FrontEND)

No, defect density not affect on all thin film materials but sometimes its depends on the method which you are using for making the thin film.

As you read in this abstract , defect density is undesirable for the thin film ,

Varying the thickness of polycrystalline Si of ZMR samples, thickness dependence of defect density in ZMR-Si films was studied. It was found that defect density of ZMR-Si film was strongly affected by thickness of polycrystalline Si. By thinning the polycrystalline Si film, defect density of ZMR-Si film was reduced to 3×106/cm2 without lowering scanning speed at ZMR process.

Dr A.Ouerdane

Dear Zulkifli,

I would like to add to the previous answers some practical considerations that may help to improve the deposited film. In order to be specific and can be helpful to you, it is advisable that you show us some pictures demonstrating such defects.

Defects in the materials have normally detracting effects on its physical performance including the mechanical, electrical and optical performance. They are classified as said before into microscopic and macroscopic defects according to their size. Macroscopic defects such as cracks and peels are not acceptable at all. If the microscopic defects increase beyond certain limit, the material would be no longer usable for electronic devices depending on the application. One has to avoid the defects formation at all with elaboration and precaution during film fabrication processing.

I would estimate that the bad adhesion of the film to substrate may be due to that the surface of your substrate is contaminated by dirties before the spin on. To reduce the defects in the deposited film you should very stringently start from very clean and dry surfaces directly before the spin on. Then you have to control the thickness very well and keep it small to avoid cracking due to the thermal miss match between the film and substrate and avoid cracking.Then anneal it in as low temperature as possible to reduce the thermal stresses at the interface and under the proper protecting gas or vacuum.You should carry out the fabrication process in clean atmosphere.

I think following these procedure and precautions will improve your film quality.

Wish you success.

I agree with the concise and clear answer by Stutzmann. I would like to add one more comment. The "quality" of a film depends on the application you have in mind. A porous film is bad if it is to be a protective layer, but it can be interesting if you wish to have a large value of the open surface area.

Certainly a poor adhesion to the substrate is a problem for whatever kind of film. This largely depends

- on the elastic mismatch between the film material and the substrate material

- on the mobility of the film material on the substrate surface and across the developing film-substrate interface (if the deposition conditions are not such that a sharp interface develops), thus on the substrate temperature and morphology and on the kinetic energy of the atoms of the film material

- on the deposition velocity

- on film thickness.

In general (with exceptions) if the substrate temperature is low, the deposited species have low kinetic energy, the deposition velocity is high, the film is more and more thick, then the probability that lattice defects develop in huge quantity increases dramatically. The resulting internal stress can lead to film failure.

In your case could you observe in your films NOT detached a curvature of the substrate+film system? With positive, or negative concavity?

Also, if some fractions of your films, even partially detached, are available, and the film is thick enough, you could perform a vertical cross section SEM observation to check the development of film microstructure with its thickness. This can be profitably correlated to defect development along the deposition.

electronic defects dictate electronic performance, obvious. Mechanical defects such as cracks can be critical when we deposit a metal or TCO. This can lead to shorts.

Definitely Yes

If the thin film is going to be an active layer in an optoelectronic devices, porosity is always bad. It allows short circuit currents, and does not favour a good charge transport. For these technical pourpouses you have to achieve the more homogenieus thin film.

It is definitely Yes. Annealing helps to remove some type of defects but not all.

In this study, μc-Si:H intrinsic layers and μc-Si:H thin film solar cells were fabricated by PECVD. The absorption coefficient (α) of the μc-Si:H thin film intrinsic layers was between 0.8 to 2.1 eV as characterized by CPM. We confirmed that the absorption coefficient at a photon energy of 1.4 eV increased with increasing crystallinity of μc-Si:H. We also found that the absorption coefficient at a photon energy of 0.9 eV decreased with increasing crystallinity, perhaps related to a reduction in the ratio of the amorphous phase in μc-Si:H. The electrical properties of μc-Si:H thin films were also influenced by both the defect density and crystallization volume fraction [6]. From this, we found, for the first time, a linear relationship between the ratio of α (1.4 eV)/α (0.9 eV) for μc-Si:H intrinsic layers, multiplied by the open-circuit voltage and short-circuit current of the corresponding μc-Si:H thin-film solar cell. Hence the ratio of α (1.4 eV)/α (0.9 eV) of a μc-Si:H thin film becomes a factor for evaluating the quality of such films for photovoltaic applications.

read more in this paper

Quality Evaluation for Microcrystalline Silicon Thin-Film Solar Cells by Single-Layer Absorption

Sheng-Hui Chen, Ting-Wei Chang, and Hsuan-Wen Wang

Electrical Properties of Dislocations in Semiconductors, R. Labusch and W. Schroter. From Dislocations in Solids, Editor F. R. N. Nabarro, Volume 5, 1980.

pp. 162.

"8. Dislocations in III-V compounds:

In III-V compounds the two face centered sublattices of the diamond structure are occupied by different kinds of atoms. The (111) slip planes are alternately occupied by atoms of group III and atoms of group V. The core of an edge type dislocation therefore may consist of atoms of group III or group V, depending on the sign of the dislocation. As first pointed out by Hansen [87], the dynamical and electrical properties of the two types should be different on account of their different cores.

This qualitative statement is fully confirmed by velocity measurements of single dislocation half loops in InSb [39, 88-90] and GaAs [90]. So far, the electrical properties of dislocations have been studied in detail only for InSb [6, 91-97].................."

pp. 183.

"Core configuration of dislocations in semiconductors:

The diamond structure has a cubic face-centered space lattice with a basis of two atoms. The stacking of {111}-planes in Si, Ge and many III-V compounds is that of the face-centered cubic structure, except that in the diamond structure each layer consists of two atomic planes. The spacings between adjacent {111}-planes are alternately narrow and wide in the ratio 1:3. Consequently there are two sets of glide planes and two sets of dislocations. If the glide occurs between two widely spaced planes, the dislocations belong to the shuffle set, if between two narrowly spaced planes, it belongs to the glide set. Complete dislocations in the shuffle set are believed to be stable, while those of the glide set are unstable with respect to a dissociation into two Shockley partials with a stacking fault between them; the reaction is of the usual type:

1/2a[110]----->1/6a[211] + 1/6a[121]............................"

With spin coating the interface (mismatch) layer is very different from other methods such as MOCVD, CVD, LPE, PLD, MBE, etc., isn't it? There is no expectation of lattice match in such applications, is there?

Lattice defects (micro) and other macro defects like voids, grain boundaries, cracks, etc. are eventually related to each other. However, the relationship to properties may be different. For example, precipitates and excess dislocations may enhance certain mechanical properties but dramatically deteriorate electrical or electro-optic properties. Key is the understanding of the correlation.

Very good discussion with lots of good information. Thanks to all participants!

The peeling of during annealing is probably due to stress formation. you can prevent this by first depositing a "glue" layer at the substrate. for this, usually a nm thick Cr layer is taken. with best regards.

I think, that this process mainly depended from two factors:

-Stress on boundary film-substrate,

-The changing of distribution concentration of defects by thickness on process of growth and thermal anneling.

For sure!

Additional practical steps to alleviate cracking of films cured after spin coating are: 1) adjust the solvent system--try a solvent with a higher boiling point; 2) use a two stage process to anneal the film--stage 1 at a relatively low temp followed by the final cure at the higher temperature. Best regards.