Hello everyone,
I've been trying to simulate a NCFET using the approach suggested from "[1] Moparthi, Sandeep, et al. "Analog and RF performance evaluation of negative capacitance SOI junctionless transistor." AEU-International Journal of Electronics and Communications (2020): 153243. and [2] Jiang, Chunsheng, Renrong Liang, and Jun Xu. "Investigation of negative capacitance gate-all-around tunnel FETs combining numerical simulation and analytical modeling." IEEE Transactions on Nanotechnology 16.1 (2016): 58-67." But, I'm facing difficulty in extracting the Q-V characteristics (ref [2] for more info) to further extend my work on NCFET using TCAD. Please, explain how to extract the Q-V characteristics from Silvaco ATLAS TCAD. TIA.
Dear Rameez Raja Shaik. May the attached content help you .
Good Luck!!!
To extract Q-V (basically gate charge vs gate voltage), there are several methods. You can perform a small-signal analysis at low frequency and plot a Cg-Vgs graph. Then you can integrate the graph to get the gate charge Qg. Also, by using an Extract command, you can extract the total charge followed by integral. Note, you will get the charge value you will need to be divided by WxL because of geometry, and after that, you can put it into LK.
we plot a Cg-Vgs to get the gate charge Qg and using an Extract
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