Hello everyone,
I am implementing Galileo E1 tracking, and I want to use FLL assisted PLL, I am using the structure given in 'Understanding GPS' by Kaplan (Page 182, figure 5.21(a)).
I try to explain what I did:
1. First I implemented FLL discriminator (ATAN2 discriminator) given again in Kaplan (Page 171, Table 5.4). But there is a small NOTE under this table telling how to choose t1 and t2 to calculate Ip1, Qp1,Ip2 and Qp2.
In that note it is written, that the two I and Q samples must be from the same navigation bit interval. My first question here is that, as my integration time is 4ms then in every iteration I will have one set of Ip and Qp, and in the next iteration I will have the second set of Ip and Qp, but both these sets are from different navigation bits because navigation bit interval for Galileo E1 is 4ms, then How can I have two sets of Ip and Qp from same navigation bit?
2. For the problem above, what I tried is that I reduced my integration time to 2ms, so that I can have two iterations per navigation bits and two corresponding sets of Ip and Qp values.
In that NOTE also, it is written that no Ip and Qp samples can be repeated in the calculation of next FLL discriminator values.
Now the question is: when I am in the second iteration I am using the Ip1 and Qp1 from the first iteration and Ip2 and Qp2 from the current(2nd) iteration, but when I will be in the third iteration, I will have to use Ip1 and Qp1 from the second iteration, that are from the previous navigation bit and also I will be using it for second time. So it means I will be repeating Ips and Qps to calculate FLL discriminator values.
I have read a lot of papers, but no one said anything about the working principle of FLL assisted PLL.
Does anyone has an idea how actually it works in every iteration and how it removes the frequency error from the incoming signal?
Thank you so much
Raza Javed
Dear Raza Javed
These links might be useful, have a look:
1. https://web.ece.ucsb.edu/~long/ece594a/PLL_intro_594a_s05.pdf
2. https://www.hindawi.com/journals/ijap/2018/6841285/
3. https://www.hindawi.com/journals/ijno/2012/651039/
Kind Regards
Qamar Ul Islam
"I have read a lot of papers, but no one said anything about the working principle of FLL assisted PLL."
The FLL assisted PLL is a standard technique used in the analog PLL. The 3 state phase frequency detector utilizing cross coupled D flip flops and V to I converter is well documented. You might want to look at its state diagram as an aid to understanding how to implement your all digital equivalent.
A phase detector only function will require a frequency sweep unless the frequency error is within the pull in range of the loop. Otherwise aided acquisition is required and this is usually accomplished by auto switching to a frequency discriminator mode. The above 3 state detector does this and so it is well worth understanding its technique.
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