Is it necessary to get a memristor layout file to calculate the area of a memristor based design using cadence virtuoso or there is an other method?
does the memristor become commercially available or not?
Dear Nahla Elazab ,
Hope you are well!
You can yourself make a physical lay out design using Cadence Lay out tools.
For the lay out rules you can use the lambda based lay out rules.
After making the lay out you can estimate the device area.
Since there is no one physical structure to the Memristor, you can either use the most common structure or you can develop one.
There is a license free lay IC physical lay out software called Lasi:https://www.electronicsforu.com/buyers-guides/software-buyers-guide/lasi-7-designing-integrated-circuits
We developed the so called the microthysitor SRAM and I invite you to further develop it. It may be promosing as the Memristors.
Please see the details of the design at:Article The Foundations of a Novel Micro – thyristor SRAM Cell
Please read it and give me feedback please.
Regarding memristor size: At the moment everybody is simply building their own memristors and defining their own layouts. The details will depend on what memristor you have specifically, but in general the active area of the device is considered the area of overlap between both electrodes and all materials in between, or in Cadence-speak: [(Top electrode) AND (Oxide 1) AND (Oxide 2) AND ... AND (Bottom electrode)].
With regard to commercial availability: TSMC produces a memristor-based memory as far as I know, but I highly doubt they will ever give access to what happens inside the memristors to anyone. I think they just sell the entire memory module, including peripheral circuits. So for practical purposes, if you want fabricated memristors you should talk to one of the groups that produces them including the Univ. of Massachusets & Stanford in the US, LETI in France, Univ. of Aachen in Germany, the univ. of Southampton in the UK and Tsinghua in China.
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