How do you define a particular process corner as Worst case corner in your CMOS circuit?

01 January 1970 0 161 Report

I have read in a few manuscripts related to STATIC memory design that, "The simulation , or write operation is performed in worst case corner." My question is How do you decide that this particular corner (SF or FF) is worst case corner for your Memory circuit? can you please mention a specific methodology or process or may be reference to decide it?

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