Ashish Sachdeva

5 Questions 38 Answers 0 Followers

Questions related from Ashish Sachdeva

Improving Critical charge in SRAM?

Which transistor is responsible for reduction in critical charge of SRAM? nMOS or pMOS? or is it the circuit design that is primarily responsible for it? Can you please help me to enlist the...

09 September 2020 898 2 View

TMSC 40nm PDK file or any other industry standard process technology file for test simulation in cadence virtuoso?

Can anyone help me with TMSC 40nm PDK files/umc 40nm PDK files or any other industry standard process technology for test simulation in cadence virtuoso? Also, the help in installing it in...

02 June 2020 3,192 0 View

How do you implement "Floating" input in a circuit?

In many CMOS circuits i have seen Floating inputs implementation. how do we practically implement the same? Beyond, how do floating input behave in a digital mechanism? A logic "low" or logic "high"?

26 May 2020 9,456 6 View

What is the impact of technology node scaling on total power dissipation of SRAM cell?

Have you compared the power dissipation(Static and dynamic) of SRAM cell on different technology nodes with similar supply voltage, material (preferably CMOS) and aspect ratio. In case it...

30 April 2020 1,711 10 View

How do you define a particular process corner as Worst case corner in your CMOS circuit?

I have read in a few manuscripts related to STATIC memory design that, "The simulation , or write operation is performed in worst case corner." My question is How do you decide that this...

01 January 1970 203 0 View